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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ICEIC : International Conference on Electronics, Informations and Communications ICEIC : 2010
- 발행연도
- 2010.6
- 수록면
- 261 - 264 (4page)
이용수
초록· 키워드
오류제보하기
The implementation of a verification environment using layered testbench is presented in this paper. SystemVerilog unifies several proven hardware design and verification languages, in the form of extensions to the Verilog HDL. The importance of verification environment based on OOP technique is increasing for high level functional verification. Due to the flexibility inherent in using OOP, code becomes simpler to use and more adaptable. The operations of Booth’s multiplier are verified in the layered testbench environment.
목차
Abstract
Ⅰ. Introduction
Ⅱ. Preliminary
Ⅲ. Verification Environment using Layered Testbench
Ⅳ. Simulation and Verification
Ⅴ. Conclusions
References
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UCI(KEPA) : I410-ECN-0101-2012-569-004077219