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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications ITC-CSCC : 2009
- 발행연도
- 2009.7
- 수록면
- 687 - 690 (4page)
이용수
초록· 키워드
오류제보하기
The implementation of a verification system using both Teal/Truss as one of high level verification environments and SystemVerilog which is hardware description and verification language is presented in this paper. SystemVerilog unifies several proven hardware design and verification languages, in the form of extensions to the Verilog HDL. Teal is class library of SystemVerilog/C++ for functional verification and Truss is an implementation of an open-source verification infrastructure based on layer approach through OOP techniques. The functionality of implemented verification system in this paper is verified using DUT which performs the operation of bilinear interpolation. Bilinear interpolation is a mathematical method for interpolating a new pixel's value with surrounding pixels. It is one of the basic operations for image resize.
목차
Abstract
1. Introduction
2. Preliminary
3. Implementation of Verification System
4. Simulation and Validation
5. Conclusion
References
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UCI(KEPA) : I410-ECN-0101-2012-569-004021459