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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.8 No.1
- 발행연도
- 2008.3
- 수록면
- 11 - 20 (10page)
이용수
초록· 키워드
오류제보하기
The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the V<SUP>th</SUP> margin for 2-bit/cell operation by ~2.5 times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the V<SUP>th</SUP> margin more than ~1.5V. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better △V<SUP>th</SUP> and V<SUP>th</SUP> margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ~10 nm below the source/drain junction.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. DEVICE STRUCTURE
Ⅲ. SIMULATION RESULTS AND DISCUSSIONS
Ⅳ. CONCLUSIONS
ACKNOWLEDGMENTS
REFERENCES
참고문헌 (19)
참고문헌 신청
1. [기타자료] - / 2006 / International Technology Roadmap for Semiconductor (ITRS; Semiconductor Industry Association, San Jose, 2006)
2. [학술대회논문] - Byung Yong Choi / 2005 / Highly scalable and reliable 2-bit/cell SONOS memory transistor beyond 50nm NVM technology using outer sidewall spacer scheme with damascene gate process / Symp. VLSI Tech. Dig., : 118 ~ 119
3. [학술지(정기간행물)] - Yong Kyu Lee / 2002 / Multilevel Vertical-Channel SONOS Nonvolatile Memory on SOI / IEEE Electron Device Lett 23 (11) : 664 ~ 666
4. [기타자료] - Masatoshi Fukuda / 2003 / Scaled 2-bit/cell SONOS type nonvolatile memory technology for sub-90nm embedded application using SiN sidewall trapping structure,”IEDM Tech. Dig. : 909 ~ 912
5. [학술지(정기간행물)] - Yong Kyu Lee / 2004 / Twin SONOS memory with 30-nm storage nodes under a merged gate fabricated with inverted sidewall and damascene process / IEEE Electron Device Lett 25 (5) : 317 ~ 319
2. [학술대회논문] - Byung Yong Choi / 2005 / Highly scalable and reliable 2-bit/cell SONOS memory transistor beyond 50nm NVM technology using outer sidewall spacer scheme with damascene gate process / Symp. VLSI Tech. Dig., : 118 ~ 119
3. [학술지(정기간행물)] - Yong Kyu Lee / 2002 / Multilevel Vertical-Channel SONOS Nonvolatile Memory on SOI / IEEE Electron Device Lett 23 (11) : 664 ~ 666
4. [기타자료] - Masatoshi Fukuda / 2003 / Scaled 2-bit/cell SONOS type nonvolatile memory technology for sub-90nm embedded application using SiN sidewall trapping structure,”IEDM Tech. Dig. : 909 ~ 912
5. [학술지(정기간행물)] - Yong Kyu Lee / 2004 / Twin SONOS memory with 30-nm storage nodes under a merged gate fabricated with inverted sidewall and damascene process / IEEE Electron Device Lett 25 (5) : 317 ~ 319
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