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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.7 No.1
- 발행연도
- 2007.3
- 수록면
- 11 - 19 (9page)
이용수
이 논문의 연구 히스토리 (3)
2007
Phase-Locked Loop with Leakage and Power/Ground Noise Compensation in 32nm Technology
Kyung Ki Kim
,
Yong-Bin Kim
,
Young Jun Lee
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2007.12
학술저널
Phase-Locked Loop with Leakage and Power/Ground Noise Compensation in 32nm Technology
Kyung Ki Kim
,
Yong-Bin Kim
,
Young Jun Lee
대한전자공학회 ISOCC
2007.10
학술대회자료
A 32㎚ and 0.9V CMOS Phase-Locked Loop with Leakage Current and Power Supply Noise Compensation
Kyung Ki Kim
,
Yong-Bin Kim
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2007.03
학술저널
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- 이 논문의 연구 히스토리 확인하기
초록· 키워드
오류제보하기
This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32㎚ predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440㎒ output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40M~725㎒ with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. PROPOSED PLL CIRCUIT DESIGN
Ⅲ. LEAKAGE COMPENSATION
Ⅳ. PSN COMPENSATION
Ⅴ. EXPERIMENTAL RESULTS
Ⅵ. CONCLUSIONS
REFERENCES
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