Analysis of a Data Recovery Circuit with Digital Oversampling Technique

Jin-Ku Kang

Journal of Electrical Engineering and information Science

1998 .10

Analysis of a Data Recovery System with Digital Oversampling Technique

Jin Ku Kang

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

1998 .01

Analysis of a Data Recovery Circuit with Digital Oversampling Technique

Jin-Ku Kang

Journal of Electrical Engineering and Information Science

1998 .10

A New Delay Model for Large Digital CMOS Circuits

Dong Wook Kim ,  Won Il Cho ,  Byung Kweon Jung

ICVC : International Conference on VLSI and CAD

1997 .01

3.125Gbps Reference-less Clock and Data Recovery using 4X Oversampling

Sung-Sop Lee ,  Hyung-Wook Jang ,  Jin-Ku Kang

대한전자공학회 학술대회

2005 .05

3.125Gbps Reference-less Clock and Data Recovery using 4X Oversampling

Hyung-Wook Jang ,  Sung-Sop Lee ,  Jin-Ku Kang

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2005 .07

2X Converse Oversampling 1.65Gb/s/ch CMOS 준 디지털 데이터 복원 회로

김길수 ,  김규영 ,  손관수 외 1명

전자공학회논문지-SD

2007 .06

A 1.25Gb/s Clock Recovery Circuit using Half-rate 4X-Oversampling PFD

Hee-Sop Song ,  Hyung-Wook Jang ,  Sung-Sop Lee 외 1명

대한전자공학회 ISOCC

2004 .10

Design of Area Efficient High Resolution CMOS Vernier Delay Line Cell

Soonyoung Lee ,  Sikanda ,  Zulqa 외 3명

대한전자공학회 학술대회

2010 .06

2X-Oversampling 2.5Gbps Clock and Data Recovery with Phase Picking Method

Yong-Hwan Moon ,  Jin-Ku Kang

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2003 .07

Design of Area Efficient High Resolution CMOS Vernier Delay Line Cell

Soonyoung Lee ,  Sikanda ,  Zulqa 외 3명

대한전자공학회 학술대회

2010 .06

고정자 치 형상에 따른 Vernier 모터의 토크 분석

김준호 ,  홍석민 ,  정상용

대한전기학회 학술대회 논문집

2018 .07

A 10-Gb/s Power and Area Efficient Clock and Data Recovery Circuit in 65-㎚ CMOS Technology

Jinsoo Rhim ,  Kwang-Chun Choi ,  Woo-Young Choi

대한전자공학회 ISOCC

2012 .11

CMOS 회로에 대한 테스트 생성 방법 ( A Test Generation Method for CMOS Circuits )

정준모 ,  장원학 ,  임인칠

대한전자공학회 학술대회

1988 .11

CMOS 회로의 테스트 생성 알고리즘 ( A Test Generation Algorithm for CMOS Circuits )

조상복 ,  임인칠

전자공학회지

1984 .11

Continuous-time Current-Mode Oversampling Modulator

이동윤 ,  김원찬

대한전자공학회 학술대회

1996 .01

Sequence Oversampling Technique based on Generative Adversarial Nets

이한규 ,  김성범

대한산업공학회 추계학술대회 논문집

2017 .11

The Vernier delay line based Time to Digital Converter with 2.5㎰ resolution for All-Digital Phased-Locked Loop

Woosong Jung ,  Deog-Kyoon Jeong

대한전자공학회 학술대회

2020 .08

DEVICE DESIGN FOR THE LOW POWER CMOS CIRCUIT

Young June Pa ,  k ,  Dae Gwan Kang 외 1명

ICVC : International Conference on VLSI and CAD

1995 .01

극 수 슬롯 수 조합에 따른 Variable Flux Vernier Machine의 특성비교

이성현 ,  김수아 ,  권중우 외 1명

대한전기학회 학술대회 논문집

2017 .07