지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- Korean Institute of Information Scientists and Engineers Journal of Electrical Engineering and Information Science Journal of Electrical Engineering and Information Science Vol.3 No.5
- 발행연도
- 1998.10
- 수록면
- 579 - 586 (8page)
이용수
초록· 키워드
오류제보하기
In this paper we analyzed a data recovery system using the oversampling technique. The input waveform is assumed to be non-return-zero (NRZ) binary signals. A finite Markov chain model is used to evaluate the steady-state phase jitter performance of the data recovery system in the presence of input noise. Theoretical results are able to predict the input signal-ta-noise ratio (SNR) versus bit error rate (BER) of the data recovery system for various oversampling ratios. The more number of samples per single bit results in the better performance on BER at the same input SNR. To achieve 10^(-11) BER, 8 times oversampling has about 2dB input signal penalty compared to 16 times oversampling. In an architectural choice of the oversampling data recovery circuit, the recovered clock can be updated in each data bit or in every multiple bits. Two different clock update schemes were analyzed and compared. The scheme updating clock in every data bit has about 1.5dB penalty against the multiple bits (4 bits) clock updating scheme with 16 times oversampling.
목차
Abstract
Ⅰ. Introduction
Ⅱ. Analysis Model
Ⅲ. Mathematical modeling and phase error calculation
Ⅳ. Phase Jitter Induced by Input Noise
Ⅴ. Bit Error Rate Analysis
Ⅵ. BER Performance of the Data Recovery Chip
Ⅶ. Conclusion
Acknowledgement
References
저자소개
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