지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.23 No.3
- 발행연도
- 2023.6
- 수록면
- 183 - 188 (6page)
- DOI
- 10.5573/JSTS.2023.23.3.183
이용수
초록· 키워드
오류제보하기
Excessively reducing gate length leads to an increase in off-state current (IOFF) due to severed short-channel effects (SCEs). 3D device architectures such as FinFETs, gate-all-around (GAA) FETs, and U-shaped channel FETs (UFETs), have been proposed in efforts to minimize the SCEs. However, increasing IOFF due to gate leakage and junction leakage is difficult to avoid. In this context, a device optimization of modern UFETs is proposed to suppress the unwanted IOFF. 3-dimensional (3-D) numerical simulations were performed to investigate the origins of the leakage current in UFETs.
목차
Abstract
I. INTRODUCTION
II. EXPERIMENTAL DETAILS
III. RESULTS AND DISCUSSIONS
IV. CONCLUSIONS
REFERENCES
참고문헌 (13)
참고문헌 신청
C. Duvvury, “A guide to short-channel effects in MOSFETs,” IEEE Circuits Syst. Mag, vol. 2, no. 6, pp. 6-10, Nov. 1986, doi: 10.1109/MCD.1986.6311897.
M. Jurczak, N. Collaert, A. Veloso, T. Hoffmann and S. Biesemans, “Review of FINFET technology,” in 2009 IEEE International SOI Conference, 2009, pp. 1-4, doi: 10.1109/SOI.2009.5318794.
J. Y. Song, W. Y. Choi, J. H. Park, J. D. Lee, and B.-G. Park, “Design optimization of gate-all-around (GAA) MOSFETs,” IEEE Trans. on Nanotechnology, vol. 5, no. 3, pp. 186-191, May 2006, doi: 10.1109/TNANO.2006.869952.
D.-W. Cha and J.-Y. Park. “Impact of Dielectrics in SOI FinFET for Lower Power Consumption in Punch-through Current-based Local Thermal Annealing,” J. Semicond. Technol. Sci, vol. 21, no. 3, pp. 222-228, Jun 2021, doi: https://doi.org/10.5573/JSTS.2021.21
S.-D. Kim, M. Guillorn, I. Lauer, P. Oldiges, T. Hook and M. -H. Na, “Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond,” in 2015 IEEE SOI-3DSubthreshold Microelectronics Technology Unified Conference (S3S),
M. Jurczak, N. Collaert, A. Veloso, T. Hoffmann and S. Biesemans, “Review of FINFET technology,” in 2009 IEEE International SOI Conference, 2009, pp. 1-4, doi: 10.1109/SOI.2009.5318794.
J. Y. Song, W. Y. Choi, J. H. Park, J. D. Lee, and B.-G. Park, “Design optimization of gate-all-around (GAA) MOSFETs,” IEEE Trans. on Nanotechnology, vol. 5, no. 3, pp. 186-191, May 2006, doi: 10.1109/TNANO.2006.869952.
D.-W. Cha and J.-Y. Park. “Impact of Dielectrics in SOI FinFET for Lower Power Consumption in Punch-through Current-based Local Thermal Annealing,” J. Semicond. Technol. Sci, vol. 21, no. 3, pp. 222-228, Jun 2021, doi: https://doi.org/10.5573/JSTS.2021.21
S.-D. Kim, M. Guillorn, I. Lauer, P. Oldiges, T. Hook and M. -H. Na, “Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond,” in 2015 IEEE SOI-3DSubthreshold Microelectronics Technology Unified Conference (S3S),
함께 읽어보면 좋을 논문
논문 유사도에 따라 DBpia 가 추천하는 논문입니다. 함께 보면 좋을 연관 논문을 확인해보세요!
-
Comparative Study of Single and Double Gate All Around Cylindrical FET Structures for High-K Dielectric Materials
Transactions on Electrical and Electronic Materials
2021 .08
-
Modeling negative and positive temperature dependence of the gate leakage current in GaN high-electron mobility transistors
[ETRI] ETRI Journal
2022 .06
-
Triple Material Surrounding Gate (TMSG) Nanoscale Tunnel FET-Analytical Modeling and Simulation
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2015 .12
-
Multi-gate BCAT Structure and Select Word-line Driver in DRAM for Reduction of GIDL
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2022 .12
-
핫-캐리어에 의해 발생하는 게이트 누설 전류의 정확한 예측을 위한 TCAD 파라미터 모델링
대한전자공학회 학술대회
2022 .06
-
Intrinsic Gate Delay를 고려한 Nanowire-FET에서의 채널 간 간격 분석
대한전자공학회 학술대회
2016 .11
-
SiC FET와 Gate Driver의 단락 보호 기능
전력전자학회 학술대회 논문집
2017 .11
-
3-D Simulation of Nanoscale SOI n-FinFET at a Gate Length of 8 nm Using ATLAS SILVACO
Transactions on Electrical and Electronic Materials
2015 .01
-
TCAD를 이용한 Gate-all-around FET 구현
대한전자공학회 학술대회
2021 .06
-
Floating Gate FET를 위한 수직 전계 효과 트랜지스터의 집적 공정 개발
대한전자공학회 학술대회
2022 .06
-
Analysis on Leakage Current of Gated Diode Memory Device and Suggestion of Improved Device Structure
대한전자공학회 학술대회
2022 .06
-
Floating Gate FET를 위한 수직 전계 효과 트랜지스터의 집적 공정 개발 및 특성 측정
대한전자공학회 학술대회
2022 .11
-
Multi-channel nanosheet FET의 gate stack 내부 work function variation 분석 연구
대한전자공학회 학술대회
2023 .06
-
Analysis of Electrical Characteristics Changes Due to Physical Parameter Variations in Dual-Gate Feedback Field Effect Transistor
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2025 .02
-
Analysis and Comparison of Intrinsic Characteristics for Single and Multi-channel Nanoplate Vertical FET Devices
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2017 .10
-
Investigation of Junction-less Tunneling Field Effect Transistor (JL-TFET) with Floating Gate
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2017 .02
-
Linearity Analysis of MoTe 2 -FET based Single Transistor AND Gate Using Non-Equilibrium Green’s Function
Transactions on Electrical and Electronic Materials
2022 .04
-
수 원자층 두께의 MoS2 채널을 가진 전계효과 트랜지스터의 게이트 전압 스트레스에 의한 I-V 특성 변화
전기전자재료학회논문지
2018 .03
-
Performance Analysis of the Gate All Around Nanowire FET with Group III–V Compound Channel Materials and High-k Gate Oxides
Transactions on Electrical and Electronic Materials
2023 .06
-
Floating Gate-FET 소자 Vector Matrix Multiplication 적용 가능성 분석
대한전자공학회 학술대회
2023 .06
이 논문의 저자 정보
최근 본 자료
댓글(0)
0
UCI(KEPA) : I410-ECN-0102-2023-569-001756796