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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 한국과학기술원 정보전자연구소 IDEC Journal of Integrated Circuits and Systems IDEC Journal of Integrated Circuits and Systems Vol.8 No.1
- 발행연도
- 2022.1
- 수록면
- 13 - 19 (7page)
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This paper presents a design methodology for high-linearity capacitively coupled (CC) continuous-time delta-sigma modulator (CTDSM). The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm2, drawing 232.2 uA at a 1.8 V supply. The proposed CC-CTDSM has a 19.4 nV/√Hz input-referred noise density, 1.9 uV offset, 0.08% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mVpp.
With -110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique
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