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논문 기본 정보

자료유형
학술저널
저자정보
Dong-Ho Lee (Chung-Ang University) Hwan-Seok Jeong (Chung-Ang University) Yeong-Gil Kim (Chung-Ang University) Myeong-Ho Kim (Samsung Display) Kyoung Seok Son (Samsung Display) Jun Hyung Lim (Samsung Display) Sang-Hun Song (Chung-Ang University) Hyuck-In Kwon (Chung-Ang University)
저널정보
대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.23 No.1
발행연도
2023.2
수록면
79 - 87 (9page)
DOI
10.5573/JSTS.2023.23.1.79

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초록· 키워드

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In this study, a quantitative analysis was conducted on the effects of channel width on electrical performance degradation induced by self-heating stress (SHS) in top-gate self-aligned coplanar indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs). From the transfer and capacitance-voltage curves obtained before and after SHS, we revealed that the electrical performance of the TFT was nonuniformly degraded along the channel length direction and the degree of this degradation was more significant in TFTs with a wider channel width. The threshold voltage shift (ΔV<SUB>TH</SUB>) under SHS in the fabricated IGZO TFT was mainly attributed to the increase in the density of shallow donor states and acceptor-like deep states in the IGZO active region and electron trapping into the fast and slow traps in the SiO<SUB>X</SUB> gate dielectric. In addition, we conducted a decomposition of the SHS-induced ΔV<SUB>TH</SUB> originated from each degradation mechanism using the subgap density of states-based ΔV<SUB>TH</SUB> decomposition technique for TFTs with different channel widths. Although every ΔV<SUB>TH</SUB> from each degradation mechanism increased as the channel width increased, increased electron trapping into the slow trap in the SiO<SUB>X</SUB> gate dielectric was the dominant reason for the larger ΔV<SUB>TH</SUB> under SHS in IGZO TFTs with a wider channel width.

목차

Abstract
I. INTRODUCTION
II. EXPERIMENTAL DETAILS
III. RESULTS AND DISCUSSION
IV. CONCLUSIONS
REFERENCES

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