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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 한국과학기술원 정보전자연구소 IDEC Journal of Integrated Circuits and Systems IDEC Journal of Integrated Circuits and Systems Vol.7 No.1
- 발행연도
- 2021.1
- 수록면
- 18 - 23 (6page)
이용수
초록· 키워드
오류제보하기
A DCO was designed for an ultra-low-jitter digital sub-sampling PLL. To suppress the enormous amount of quantization noise, a very fine frequency resolution is critical. Also, the phase noise of an LC VCO itself is crucial for ultra-low-jitter applications. For high-performance LC VCO design, a basic insight into the oscillator is needed. The proposed DCO consists of a string-type RDAC, MASH 1-1 DSM, and CMOS-type cross-coupled LC VCO. The frequency resolution is significantly increased by using the DSM. The proportional path has a 17-bit resolution, while the integral path has an 18-bit resolution. The DSM operates at 400 MHz, and its quantization noise is canceled by the 2nd-order low-pass filter at the output of the DAC. By adopting 2nd-order noise shaping, the quantization noise at the PLL output is negligible. The DAC was designed with a string resistor topology for its design simplicity and relieved target specifications. The DCO has a 12 to 14.5 GHz frequency tuning range. The phase noise at a 1 MHz offset frequency is –109 dBc/Hz at a 14-GHz output. The average power consumption is 5.5 mW. The calculated FOM at a 1-MHz offset frequency is –184.5 dB.
목차
등록된 정보가 없습니다.
참고문헌 (6)
참고문헌 신청
L. Fanori / 2010 / 3.3GHz DCO with a frequency resolution of 150Hz for all-digital PLL / Digest of Technical Papers - IEEE International Solid-State Circuits Conference 53:48~49
Y. Chen / 2007 / A 9 GHz dual-mode digitally controlled oscillator for GSM/UMTS transceivers in 65 nm CMOS / 2007 IEEE Asian Solid-State Circuits Conference, ASSCC :432~435
Z. Huang / 2015 / A dithering-less 54.79-to 63.16GHz DCO with 4-Hz frequency resolution using an exponentially-scaling C-2C switched-capacitor ladder / IEEE Symposium on VLSI Circuits, Digest of Technical Papers :C234~C235
B. Razavi / RF microelectronics / Pearson
M. Babaie / 2013 / A class-F CMOS oscillator / IEEE J. Solid-State Circuits 48(12):3120~3133
Y. Chen / 2007 / A 9 GHz dual-mode digitally controlled oscillator for GSM/UMTS transceivers in 65 nm CMOS / 2007 IEEE Asian Solid-State Circuits Conference, ASSCC :432~435
Z. Huang / 2015 / A dithering-less 54.79-to 63.16GHz DCO with 4-Hz frequency resolution using an exponentially-scaling C-2C switched-capacitor ladder / IEEE Symposium on VLSI Circuits, Digest of Technical Papers :C234~C235
B. Razavi / RF microelectronics / Pearson
M. Babaie / 2013 / A class-F CMOS oscillator / IEEE J. Solid-State Circuits 48(12):3120~3133
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