지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2021.11
- 수록면
- 919 - 924 (6page)
- DOI
- 10.5302/J.ICROS.2021.21.0133
이용수
초록· 키워드
오류제보하기
In this paper, we present a low-power 24 ㎓ CMOS LNA (Low Noise Amplifier) for automotive collision avoidance radar. The proposed circuit was fabricated using the 65-nm RF CMOS technology and powered by a 1.2 V supply. To decrease the power consumption and increase the voltage gain, a cascode scheme was implemented in this circuit, and it was optimized to decrease the noise figure. Compared to the recently reported LNA, our proposed LNA showed the lowest power consumption and noise figure of 4.59 ㎽ and 2.98 ㏈, respectively, with a high voltage gain of 24.3 ㏈. Additionally, it was designed with the smallest chip area of 0.6×0.6 ㎟ and a core cell of 0.31×0.35 ㎟ without pads.
목차
Abstract
Ⅰ. Introduction
Ⅱ. Circuit Design and Analysis
Ⅲ. Results and Discussions
Ⅳ. Conclusions
REFERENCES
참고문헌 (17)
참고문헌 신청
J.-I. Chun, Y.-J. Choi, and J.-Y. Ryu, “Design of a lowpower 12-bit 1MSps SAR Analog-to-Digital converter,” Journal of Institute of Control, Robotics and Systems (in Korean), vol. 27, no. 1, pp. 26-31, Jan. 2021.
S.-H. Noh and J.-Y. Ryu, “Linearity enhancement technique for GHz-Band LNA,” International Journal of Applied Engineering Research, vol. 12, no. 19, pp. 9116-9119, Oct. 2017.
H. Rastegar and J.-Y. Ryu, “An integrated high linearity CMOS receiver frontend for 24 GHz applications,” Journal of Semiconductor Technology and Science, vol. 16, no. 5, pp. 595-604, Oct. 2016.
H. Rastegar and J.-Y. Ryu, “A broadband low noise amplifier with built-in linearizer in 0.13 μm CMOS process,” Microelectronics Journal, vol. 46, no. 8, pp. 698-705, Aug. 2015.
W.-H. Chen, G. Liu, B. Zdravko, and A. M. Niknejad, “A highly linear broadband CMOS LNA employing noise and distortion cancellation,” IEEE Journal of Solid-State Cciruits, vol. 43, no. 5, pp. 1164-1176. May 2008.
S.-H. Noh and J.-Y. Ryu, “Linearity enhancement technique for GHz-Band LNA,” International Journal of Applied Engineering Research, vol. 12, no. 19, pp. 9116-9119, Oct. 2017.
H. Rastegar and J.-Y. Ryu, “An integrated high linearity CMOS receiver frontend for 24 GHz applications,” Journal of Semiconductor Technology and Science, vol. 16, no. 5, pp. 595-604, Oct. 2016.
H. Rastegar and J.-Y. Ryu, “A broadband low noise amplifier with built-in linearizer in 0.13 μm CMOS process,” Microelectronics Journal, vol. 46, no. 8, pp. 698-705, Aug. 2015.
W.-H. Chen, G. Liu, B. Zdravko, and A. M. Niknejad, “A highly linear broadband CMOS LNA employing noise and distortion cancellation,” IEEE Journal of Solid-State Cciruits, vol. 43, no. 5, pp. 1164-1176. May 2008.
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