지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.21 No.5
- 발행연도
- 2021.10
- 수록면
- 356 - 363 (8page)
- DOI
- 10.5573/JSTS.2021.21.5.356
이용수
초록· 키워드
오류제보하기
A concurrent dual-band CMOS partial feedback LNA optimizing noise and input reflection coefficient (S<SUB>11</SUB>) at both 2.4 and 5.2 GHz frequency bands is designed using a 65-nm CMOS process for advanced WLAN applications. The inverter-based input transconductance stage directly drives two parallel cascode transistors with 2.4 and 5.2 GHz LC loads, and the output signals splitting into two resonators are combined through a complementary source follower (CSF). Based on an analytical study on the optimum noise impedance (Z<SUB>opt</SUB>) and minimum noise figure (NF<SUB>min</SUB>) of the proposed concurrent LNA circuit topology, the concurrent dual-band input matching network is designed in order to achieve low noise figure (NF) around NF<SUB>min</SUB> at both operating frequencies. By employing a partial resistive feedback between 2.4 GHz LC resonator and input transconductance stage through a CSF, an imperfect S11 of the proposed LNA at 2.4 GHz is improved at the expense of a slight increase of NF. In the simulation, the designed LNA achieved forward gain (S<SUB>21</SUB>) of 14 and 15.5 dB, NF of 1.6 and 2.2 dB, and S11 of -11.2 and -10.3 dB at 2.4 and 5.2 GHz, respectively. The power consumption of the designed LNA is 7.7 mW from a 1.2 V supply voltage.
목차
Abstract
I. INTRODUCTION
II. DESIGN OF 2.4/5.2 GHZ CONCURRENT DUAL-BAND LNA
III. SIMULATION RESULTS
IV. CONCLUSIONS
REFERENCES
참고문헌 (13)
참고문헌 신청
M. Zargari, M. Terrovitis, S. H. -M. Jen, B. J. Kaczynski, MeeLan Lee, M. P. Mack, S. S. Mehta, S. Mendis, K. Onodera, H. Samavati, W. W. Si, K. Singh, A. Tabatabaei, D. Weber, D. K. Su, and B. A. Wooley, “A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2239-2249, Dec. 2004.
T. Maeda, N. Matsuno, S. Hori, T. Yamase, T. Tokairin, K. Yanagisawa, H. Yano, R. Walkington, K. Numata, N. Yoshida, Y. Takahashi, and H. Hida, “A low-power dual-band triple-mode WLAN CMOS transceiver,” IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 2481-2490, Nov. 2006.
S. Gross, T. Maimon, F. Cossoy, M. Ruberto, G. Normatov, A. Rivkind, N. Telzhensky, R. Banin, O. Ashckenazi, A. Ben-Bassat, S. Zaguri, G. Hara, M. Zajac, N. shahar, S. Shahaf, H. Yousef, E. Mor, Y. Eliat, A. Nazimov, Z. Beer, A. Fridman, and O. Degani, “Dual-band CMOS transceiver with highly integrated front-end for 450Mb/s 802.11 n systems,” in Proc. IEEE RFIC, Anaheim, CA, USA, May. 2010, pp. 431-434.
X. Yi, K. Yang, Z. Liang, B. Liu, K. Devrishi, C.C. Boon, C. Li, G. Feng, D. Regev, S. Shilo, F. Meng, H. Liu, J. Sun, G. Hu, and Y. Miao, “A 65nm CMOS carrier-aggregation transceiver for IEEE 802.11 WLAN applications,” in Proc. IEEE RFIC, San Francisco, CA, USA, May. 2016, pp. 67-70.
S. Hwu, and B. Razavi, “An RF receiver for intraband carrier aggregation,” IEEE J. Solid-State Circuits, vol. 50, no. 4, pp. 946-961, April. 2006.
T. Maeda, N. Matsuno, S. Hori, T. Yamase, T. Tokairin, K. Yanagisawa, H. Yano, R. Walkington, K. Numata, N. Yoshida, Y. Takahashi, and H. Hida, “A low-power dual-band triple-mode WLAN CMOS transceiver,” IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 2481-2490, Nov. 2006.
S. Gross, T. Maimon, F. Cossoy, M. Ruberto, G. Normatov, A. Rivkind, N. Telzhensky, R. Banin, O. Ashckenazi, A. Ben-Bassat, S. Zaguri, G. Hara, M. Zajac, N. shahar, S. Shahaf, H. Yousef, E. Mor, Y. Eliat, A. Nazimov, Z. Beer, A. Fridman, and O. Degani, “Dual-band CMOS transceiver with highly integrated front-end for 450Mb/s 802.11 n systems,” in Proc. IEEE RFIC, Anaheim, CA, USA, May. 2010, pp. 431-434.
X. Yi, K. Yang, Z. Liang, B. Liu, K. Devrishi, C.C. Boon, C. Li, G. Feng, D. Regev, S. Shilo, F. Meng, H. Liu, J. Sun, G. Hu, and Y. Miao, “A 65nm CMOS carrier-aggregation transceiver for IEEE 802.11 WLAN applications,” in Proc. IEEE RFIC, San Francisco, CA, USA, May. 2016, pp. 67-70.
S. Hwu, and B. Razavi, “An RF receiver for intraband carrier aggregation,” IEEE J. Solid-State Circuits, vol. 50, no. 4, pp. 946-961, April. 2006.
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