지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.21 No.5
- 발행연도
- 2021.10
- 수록면
- 311 - 321 (11page)
- DOI
- 10.5573/JSTS.2021.21.5.311
이용수
초록· 키워드
오류제보하기
In this paper, we propose periodic slit ground structure (PSG) to improve the signal integrity of multilevel signals at high data rate such as MIPI C-PHY. Periodic slits are added in the upper and lower ground planes of the stripline structure, without adding additional layers or increasing area, to reduce crosstalk among neighboring lines. The proposed PSG structure can effectively improve the eye-diagram, especially eye height (EH) in multilevel signaling. The effectiveness of the proposed structure is validated through simulation and measurement of PCB-flexible printed circuit board (FPCB)-PCB structure that emulates the interconnected system of MIPI C-PHY signal transmission in a mobile system. The measurements from the test structures show that at a 2.5 Gsps data rate condition, the PSG structures show improvement in EH and eye width (EW) by 38.6% and 9.7%, respectively, compared to stripline structures. The proposed idea can be generally applied in PCB designs that will be used in high speed multilevel signal transmission to improve EH.
목차
Abstract
I. INTRODUCTION
II. PROPOSED PCB STRUCTURE
III. FPCB STRUCTURE DESIGN
IV. SIMULATION AND MEASUREMENT RESULTS
V. CONCLUSIONS
REFERENCES
참고문헌 (20)
참고문헌 신청
S. Y. Kim and K. Y. Lee, “A 1.248 Gb/s - 2.918 Gb/s Low-Power Receiver for MIPI-DigRF MPHY with a Fast Settling Fully Digital Frequency Detection Loop in 0.11 m CMOS,” Journal of Semiconductor Technology and Science, vol. 15, no. 4, pp. 506-517, 2015.
K. Hu et al., “A 0.6 mW/Gb/s, 6.4-7.2 Gb/s Serial Gb/s Serial Link Receiver Using Local Injectionlocked Ring Oscillator in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 899-908, Apr. 2010.
P. Lancheres and M. Hafed, “The MIPI C-PHY Standard: A Generalized Multiconductor Signaling Scheme,” IEEE Solid-State Circuits Magazine, vol. 11, no. 2, pp. 69-77, 2019.
S. W. Choi and Y. C. Jang, “A MIPI Receiver Bridge Chip Supporting 5-Gb/s/lane D-PHY and 3- Gsymbol/s/lane C-PHY,” Journal of Semiconductor Technology and Science, vol. 20, no. 1, pp. 29-40, 2020.
MIPI C-PHY. [online] Available at: https://www.mipi.org/specifications/c-phy [Accessed 24 Dec. 2019].
K. Hu et al., “A 0.6 mW/Gb/s, 6.4-7.2 Gb/s Serial Gb/s Serial Link Receiver Using Local Injectionlocked Ring Oscillator in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 899-908, Apr. 2010.
P. Lancheres and M. Hafed, “The MIPI C-PHY Standard: A Generalized Multiconductor Signaling Scheme,” IEEE Solid-State Circuits Magazine, vol. 11, no. 2, pp. 69-77, 2019.
S. W. Choi and Y. C. Jang, “A MIPI Receiver Bridge Chip Supporting 5-Gb/s/lane D-PHY and 3- Gsymbol/s/lane C-PHY,” Journal of Semiconductor Technology and Science, vol. 20, no. 1, pp. 29-40, 2020.
MIPI C-PHY. [online] Available at: https://www.mipi.org/specifications/c-phy [Accessed 24 Dec. 2019].
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