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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 IEIE Transactions on Smart Processing & Computing IEIE Transactions on Smart Processing & Computing Vol.10 No.4
- 발행연도
- 2021.8
- 수록면
- 309 - 314 (6page)
- DOI
- 10.5573/IEIESPC.2021.10.4.309
이용수
초록· 키워드
오류제보하기
This paper proposes a new cost-effective approximate adder that exploits OR operation and zero truncation. The proposed approximation technique reduces the hardware cost significantly while maintaining comparable computation accuracy. The proposed adder achieved 48%, 51%, and 48% reductions in the area, delay, and power, respectively, compared to a traditional adder when implemented in 32-nm CMOS technology. The proposed design could also enhance the normalized mean error distance up to 29% compare to the approximate adders considered in this paper. The adder showed an excellent tradeoff performance between the hardware and computation accuracy. Furthermore, the proposed adder was adopted in a digital image processing application, and the benefit of the proposed adder is demonstrated.
목차
Abstract
1. Introduction
2. Proposed Approximate Adder
3. Experimental Results
4. Conclusions
References
참고문헌 (22)
참고문헌 신청
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Q. Wang, P. Li, and Y. Kim, “A Parallel Digital VLSI Architecture for Integrated Support Vector Machine Training and Classification,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 8, pp. 1471-1474, 2015.
Y. Yang and Y. Kim, "Approximate Digital Leaky Integrate-and-fire Neurons for Energy Efficient Spiking Neural Networks," IEIE Trans. Smart Process. Comput., vol. 9, no. 3, pp. 252-259, 2020. Article (CrossRef Link)
Y. Kim, Y. Zhang, and P. Li, “A Reconfigurable Digital Neuromorphic Processor with Memristive Synaptic Crossbar for Cognitive Computing,” J. Emerg. Technol. Comput. Syst., vol. 11, no. 4, pp.38:1-38:25, 2015. Article (CrossRef Link)
Q. Wang, Y. Kim, and P. Li, “Architectural Design Exploration for Neuromorphic Processors with Memristive Synapses”, IEEE Int. Conf. Nanotechnology, pp. 962-996, Aug. 2014.
Q. Wang, P. Li, and Y. Kim, “A Parallel Digital VLSI Architecture for Integrated Support Vector Machine Training and Classification,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 8, pp. 1471-1474, 2015.
Y. Yang and Y. Kim, "Approximate Digital Leaky Integrate-and-fire Neurons for Energy Efficient Spiking Neural Networks," IEIE Trans. Smart Process. Comput., vol. 9, no. 3, pp. 252-259, 2020. Article (CrossRef Link)
Y. Kim, Y. Zhang, and P. Li, “A Reconfigurable Digital Neuromorphic Processor with Memristive Synaptic Crossbar for Cognitive Computing,” J. Emerg. Technol. Comput. Syst., vol. 11, no. 4, pp.38:1-38:25, 2015. Article (CrossRef Link)
Q. Wang, Y. Kim, and P. Li, “Architectural Design Exploration for Neuromorphic Processors with Memristive Synapses”, IEEE Int. Conf. Nanotechnology, pp. 962-996, Aug. 2014.
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