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논문 기본 정보

자료유형
학술저널
저자정보
Yi Zhang (Nanjing University of Posts and Telecommunications) Xiaopeng Li (Nanjing University of Posts and Telecommunications) Youtao Zhang (Nanjing University of Posts and Telecommunications) Yufeng Guo (Nanjing University of Posts and Telecommunications) Ying Zhang (Nanjing University of Posts and Telecommunications) Hao Gao (Eindhoven University of Technology)
저널정보
대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.21 No.6
발행연도
2021.12
수록면
438 - 448 (11page)
DOI
10.5573/JSTS.2021.21.6.438

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초록· 키워드

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Ultra-high-speed full adder is the bottleneck in a tens of GHz Direct digital synthesizer (DDS). In this paper, a 32.2 GHz, 1bit full adder in a 0.7 μm InP double hetero-junction bipolar transistor (DHBT) technology is presented. In such a high-speed circuit, signal integrity is a crucial issue. Therefore, a transmission line equivalent (TLE) method is proposed. With the TLE method, the design of the full adder could be simplified with good accuracy. The synchronous latch is combined with adding operation to improve the calculation speed. A single-level parallel-gated circuit is designed using majority decision algorithm to reduce power consumption. Measurement results show that the maximum clock frequency of the full adder is 32.2-GHz, and the overall power consumption is 350 mW. The full adder is successfully adopted in a 17 GHz, 8 bit DDS which can synthesize sin-wave outputs from 66.41 MHz to 8.5 GHz in 66.41 MHz steps with an average Spurious-Free Dynamic Range (SFDR) of -18.1 dBc.

목차

Abstract
I. INTRODUCTION
II. FULL ADDER CIRCUIT DESIGN
III. TLE DESIGN METHODOLOGY
IV. MEASUREMENT RESULTS
V. CONCLUSIONS
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