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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.21 No.2
- 발행연도
- 2021.4
- 수록면
- 166 - 173 (8page)
- DOI
- 10.5573/JSTS.2021.21.2.166
이용수
초록· 키워드
오류제보하기
This paper presents a novel approach to solve the time constraint issue of DFE with PAM4 signaling. By using track and hold operation to sample signals of the same level at two points, the time constraint of 1 UI in direct DFE can be extended to 1.5UI. The FIR-tap employs LVDS structure to maintain common voltage and SS-LMS algorithm is used to obtain the optimal tap weight. The first post-cursor ISI cancellation is done by the LVDS tap and a sufficient settling time is provided by the proposed DFE. The proposed structure may eliminate the loop unrolling speculative DFE for PAM-4, which leads to less hardware for PAM-4 DFE implementation. A PAM-4 serial link using the proposed DFE was designed in a 65nm CMOS technology and analyzed. Channels with 11.9 dB and 13.8 dB losses were compensated through CTLE and the proposed 1 tap DFE, and simulation results demonstrate the time constraint can be extended without deterioration of the eye opening.
목차
Abstract
I. INTRODUCTION
II. PROPOSED DFE WITH EXTENDED TIME CONSTRAINT
III. EXPERIMENTAL RESULTS
V. CONCLUSIONS
REFERENCES
참고문헌 (12)
참고문헌 신청
A. Roshan-Zamir, O. Elhadidy, H. Yang and S. Palermo, “A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS,” Solid-State Circuits, IEEE Journal of, Vol. 52, No. 4, pp. 2430-2447, Sept., 2017
J. Im et al., “A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET,” Solid-State Circuits, IEEE Journal of, VOL. 52, No. 12, pp. 3486-3502, Dec., 2017
R. Payne et al., “A 6.25-Gb/s binary transceiver in 0.13-/spl mu/m CMOS for serial data transmission across high loss legacy backplane channels,” Solid-State Circuits, IEEE Journal of, Vol. 40, No. 12, pp. 2646-2657, Dec., 2005
A. Roshan-Zamir et al., “A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS,” Solid-State Circuits, IEEE Journal of, Vol. 54, No. 3, pp. 672-684, Mar., 2019
M. Dolan and F. Yuan, “An adaptive edge decision feedback equalizer with 4PAM signaling,” Circuit and Systems, 2017, MWSCAS 2017, 60th IEEE International Midwest Symposium on, pp. 535-538, MA., 2017.
J. Im et al., “A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET,” Solid-State Circuits, IEEE Journal of, VOL. 52, No. 12, pp. 3486-3502, Dec., 2017
R. Payne et al., “A 6.25-Gb/s binary transceiver in 0.13-/spl mu/m CMOS for serial data transmission across high loss legacy backplane channels,” Solid-State Circuits, IEEE Journal of, Vol. 40, No. 12, pp. 2646-2657, Dec., 2005
A. Roshan-Zamir et al., “A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS,” Solid-State Circuits, IEEE Journal of, Vol. 54, No. 3, pp. 672-684, Mar., 2019
M. Dolan and F. Yuan, “An adaptive edge decision feedback equalizer with 4PAM signaling,” Circuit and Systems, 2017, MWSCAS 2017, 60th IEEE International Midwest Symposium on, pp. 535-538, MA., 2017.
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