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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.16 No.5
- 발행연도
- 2016.10
- 수록면
- 650 - 656 (7page)
이용수
초록· 키워드
오류제보하기
Voltage controlled oscillator (VCO) is widely used circuit component in high-performance microprocessors and modern communication systems as a frequency source. In present work, VCO designs using the different combination of NAND gates with three transistors and CMOS inverter are reported. Three, five and seven stages ring VCO circuits are designed. Coarse and fine tuning have been done using two different supply sources. The frequency with coarse tuning varies from 3.31 GHz to 5.60 GHz in three stages, 1.77 GHz to 3.26 GHz in five stages and 1.27 GHz to 2.32 GHz in seven stages VCO respectively. Moreover, for fine tuning frequency varies from 3.70 GHz to 3.94 GHz in three stages, 2.04 GHz to 2.18 GHz in five stages and 1.43 GHz to 1.58 GHz in seven stages VCO respectively. Results of power consumption and phase noise for the VCO circuits are also been reported. Results of proposed VCO circuits have been compared with previously reported circuits and present circuit approach show significant improvement.
목차
Abstract
I. INTRODUCTION
II. CIRCUIT DESCRIPTION
III. RESULTS AND DISCUSSIONS
IV. CONCLUSIONS
REFERENCES
참고문헌 (25)
참고문헌 신청
[학술지(정기간행물)] - Hsu, T. Y. / 2001 / Design and analysis of a portable high-speed clock generator / IEEE Transactions on Circuits and Systems II:Analog and Digital Signal Processing 48 (4) : 367 ~ 375
[학술지(정기간행물)] - Boerstler, D. W. / 1999 / A low-jitter PLL clock generator for microprocessors with lock range of 340-612MHz / IEEE Journal of Solid-State Circuits 34 (4) : 513 ~ 519
[학술지(정기간행물)] - Staszewski, R. B. / 2005 / Phase-domain all-digital phase-locked loop / IEEE Transactions on Circuits and Systems II: Express Briefs 52 (3) : 159 ~ 163
[학술지(정기간행물)] - Lee, S. Y. / 2008 / Analysis and implementation of a 0.9-V voltage-controlled oscillator with low phase noise and low power dissipation / IEEE Transactions on Circuits and Systems II: Express Briefs 55 (7) : 624 ~ 627
[학술지(정기간행물)] - Craninckx, J. / 1995 / A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator with prescaler / IEEE Journal of Solid-State Circuits 30 (12) : 1474 ~ 1482
[학술지(정기간행물)] - Boerstler, D. W. / 1999 / A low-jitter PLL clock generator for microprocessors with lock range of 340-612MHz / IEEE Journal of Solid-State Circuits 34 (4) : 513 ~ 519
[학술지(정기간행물)] - Staszewski, R. B. / 2005 / Phase-domain all-digital phase-locked loop / IEEE Transactions on Circuits and Systems II: Express Briefs 52 (3) : 159 ~ 163
[학술지(정기간행물)] - Lee, S. Y. / 2008 / Analysis and implementation of a 0.9-V voltage-controlled oscillator with low phase noise and low power dissipation / IEEE Transactions on Circuits and Systems II: Express Briefs 55 (7) : 624 ~ 627
[학술지(정기간행물)] - Craninckx, J. / 1995 / A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator with prescaler / IEEE Journal of Solid-State Circuits 30 (12) : 1474 ~ 1482
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