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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.20 No.1
- 발행연도
- 2020.2
- 수록면
- 41 - 46 (6page)
- DOI
- 10.5573/JSTS.2020.20.1.041
이용수
초록· 키워드
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In this paper, the influences of design parameters on the line-edge roughness (LER) effects in a nanowire tunnel field-effect transistor (TFET) and a metal-oxide-semiconductor FET (MOSFET) have been discussed with the help of technology computer-aided design simulation. The strength of LER effects are quantitatively examined by correlation coefficients (R) between electrical performances and variations of nanowire dimensions; 1) threshold voltage (V<SUB>th</SUB>) vs. channel volume, 2) ONstate current (I<SUB>ON</SUB>) vs. channel volume, 3) V<SUB>th</SUB> vs. source-channel junction area, and 4) I<SUB>ON</SUB> vs. sourcechannel junction area. According to the simulation results, the nanowire MOSFET shows the similar values from 0.47-R to 0.74-R for all cases. On the other hand, the nanowire TFET only depends on the variation in the source-channel junction area with R more than 0.4.
목차
Abstract
I. INTRODUCTION
II. SIMULATION CONDITIONS
III. RESULTS AND DISCUSSION
IV. CONCLUSIONS
REFERENCES
참고문헌 (27)
참고문헌 신청
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E. J. Nowak, “Maintaining the benefits of CMOS scaling when scaling bogs down,” IBM J. Res. Dev., Vol. 46, No. 2.3, pp. 169-180, 2002.
P. Y. Wang and B. Y. Tsui, “Band engineering to improve average subthreshold swing by suppressing low electric field band-to-band tunneling with epitaxial tunnel layer tunnel FET structure,” IEEE Trans. Nanotechnol., Vol. 15, No. 1, pp. 74-79, 2016.
A. Mishra, M. Pattanaik, and V. Sharma, “Double gate vertical tunnel FET for hybrid CMOS-TFET based low standby power logic circuits,” 2013 Annual International Conference on Emerging Research Areas and 2013 International Conference on Microelectronics, Communications and Renewable Energy, 2013, pp. 1-4.
S. Cristoloveanu, J. Wan, and A. Zaslavsky, “A review of sharp-switching devices for ultra-low power applications,” IEEE Journal of the Electron Devices Society. 2016.
E. J. Nowak, “Maintaining the benefits of CMOS scaling when scaling bogs down,” IBM J. Res. Dev., Vol. 46, No. 2.3, pp. 169-180, 2002.
P. Y. Wang and B. Y. Tsui, “Band engineering to improve average subthreshold swing by suppressing low electric field band-to-band tunneling with epitaxial tunnel layer tunnel FET structure,” IEEE Trans. Nanotechnol., Vol. 15, No. 1, pp. 74-79, 2016.
A. Mishra, M. Pattanaik, and V. Sharma, “Double gate vertical tunnel FET for hybrid CMOS-TFET based low standby power logic circuits,” 2013 Annual International Conference on Emerging Research Areas and 2013 International Conference on Microelectronics, Communications and Renewable Energy, 2013, pp. 1-4.
S. Cristoloveanu, J. Wan, and A. Zaslavsky, “A review of sharp-switching devices for ultra-low power applications,” IEEE Journal of the Electron Devices Society. 2016.
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