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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.22 No.2
- 발행연도
- 2022.4
- 수록면
- 61 - 68 (8page)
- DOI
- 10.5573/JSTS.2022.22.2.61
이용수
초록· 키워드
오류제보하기
This paper suggests a doping-less TFET that shows high performance in low power circumstances and its electrical characteristics are analyzed. The doping-less TFET’s gate insulator consists of ONO (SiO₂-Si₃N₄-SiO₂) triple dielectric. When programmed, the tunnel barrier is formed by electron charge traps of nitride region. Then, the tunnel barrier is adjusted by trapped electrons in silicon nitride region. Therefore, it is possible to control the electrical characteristics of the device by controlling the number of electrons trapped in the nitride region by adjusting the program time. However, since the device is made of doping-less, the depletion area has increased as the substrate thickness due to the loss of control of the gate. So, the thinner the substrate thickness of the device, the better the efficiency. In the case of thin substrate thickness, TCAD simulation was per-formed by applying a 5 nm of substrate thickness because the thinner the substrate thickness of the device, the more efficient it is. As a result, the proposed device shows low subthreshold swing (SS) of 29.01 ㎷/decade at 0.5 V of V<SUB>DS</SUB> in the transfer curves. Then, the proposed TFET can control the electrical characteristics with program time and can be driven with low power due to having a low SS.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. SIMULATION CONDITION
Ⅲ. RESULTS AND DISCUSSION
Ⅳ. CONCLUSIONS
REFERENCES
참고문헌 (41)
참고문헌 신청
B. Yu et al., “FinFET scaling to 10 nm gate length,” in Technical Digest - International Electron Devices Meeting, 2002, pp. 251-254, doi: 10.1109/IEDM.2002.1175825.
N. Singh et al., “High-performance fully depleted silicon nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices,” IEEE Electron Device Lett., vol. 27, no. 5, pp. 383-386, 2006, doi: 10.1109/LED. 2006.873381.
X. Huang et al., “Sub 50-nm FinFET: PMOS,” in Technical Digest - International Electron Devices Meeting, 1999, pp. 67-70, doi: 10.1109/iedm.1999. 823848.
D. Hisamoto et al., “FinFET—A self-aligned double-gate MOSFET scalable to 20 nm,” IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, 2000, doi: 10.1109/16.887014.
S. Bangsaruntip et al., “High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling,” in Technical Digest - International Electron Devices Meeting, IEDM, 2009, pp. 1-4, doi: 10.1109/IEDM. 2009.5424364.
N. Singh et al., “High-performance fully depleted silicon nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices,” IEEE Electron Device Lett., vol. 27, no. 5, pp. 383-386, 2006, doi: 10.1109/LED. 2006.873381.
X. Huang et al., “Sub 50-nm FinFET: PMOS,” in Technical Digest - International Electron Devices Meeting, 1999, pp. 67-70, doi: 10.1109/iedm.1999. 823848.
D. Hisamoto et al., “FinFET—A self-aligned double-gate MOSFET scalable to 20 nm,” IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, 2000, doi: 10.1109/16.887014.
S. Bangsaruntip et al., “High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling,” in Technical Digest - International Electron Devices Meeting, IEDM, 2009, pp. 1-4, doi: 10.1109/IEDM. 2009.5424364.
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