지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 한국전기전자재료학회 Transactions on Electrical and Electronic Materials Transactions on Electrical and Electronic Materials 제11권 제1호
- 발행연도
- 2010.1
- 수록면
- 20 - 23 (4page)
이용수
초록· 키워드
오류제보하기
The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and measurements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the pause period. A high voltage lateral double diffused metal-oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the 0.18 µm standard CMOS process, with an AFE core size of 350 µm × 230 µm. The measurement results show that the DPLL, using a demodulator output signal, generates a constant 1.695 MHz clock during the pause period of the 100% ASK signal.
목차
등록된 정보가 없습니다.
참고문헌 (9)
참고문헌 신청
B. Razavi / 1996 / Monolithic Phase-Locked Loops and Clock Recovery Circuits :Theory and Design / IEEE Press : 327 ~
H. Yu / 2003 / / IEEE international solid-state circuits conference (ISSCC). Digest of technical papers : 194 ~
International Organization for Standardization and International Electrotechnical Commission / 2008 / ISO/IEC 14443. Identification Cards-Contactless Integrated Circuit Cards-Proximity
K. Finkenzeller / 2003 / RFID Handbook: Fundamentals and Applications in Contactless Smart Cards and Identification, 2nd ed / John Wiley and Sons : 183 ~
Kee-Yeol Na / 2009 / Fabricating high performance n-channel lateral double diffused metal?oxide?semiconductor transistors utilizing the shallow trench isolation as a salicide
H. Yu / 2003 / / IEEE international solid-state circuits conference (ISSCC). Digest of technical papers : 194 ~
International Organization for Standardization and International Electrotechnical Commission / 2008 / ISO/IEC 14443. Identification Cards-Contactless Integrated Circuit Cards-Proximity
K. Finkenzeller / 2003 / RFID Handbook: Fundamentals and Applications in Contactless Smart Cards and Identification, 2nd ed / John Wiley and Sons : 183 ~
Kee-Yeol Na / 2009 / Fabricating high performance n-channel lateral double diffused metal?oxide?semiconductor transistors utilizing the shallow trench isolation as a salicide
함께 읽어보면 좋을 논문
논문 유사도에 따라 DBpia 가 추천하는 논문입니다. 함께 보면 좋을 연관 논문을 확인해보세요!
-
미세 신호 센서를 위한 초저 잡음 AFE 회로
대한전자공학회 학술대회
2019 .06
-
5-GHz 2nd order Charge-Pump Phase-Locked Loop with 100MHz reference clock의 설계
대한전자공학회 학술대회
2017 .06
-
DPLL을 이용한 클럭 및 데이터 복구회로 설계 ( A DPLL-Based Clock/Data Recovery Circuit Design )
CAD 및 VLSI 설계연구회지
1996 .01
-
CCD 이미지 센서용 AFE 설계
대한전자공학회 학술대회
2011 .04
-
부위별 다중주파수기반 생체전기 임피던스 분석법을 활용한 체성분 측정용 AFE 칩 설계
대한전자공학회 학술대회
2019 .11
-
커패시터 멀티플라이어를 이용한 디지털 위상 고정 루프(DPLL)의 설계
대한전자공학회 학술대회
2013 .07
-
A DPLL with a Modified Phase Frequency Detector to Reduce Lock Time
전자공학회논문지
2013 .10
-
고압배전선로 전력선 통신용 AFE 개발
한국통신학회 학술대회논문집
2002 .11
-
A 40 Gb/s Clock and Data Recovery Module with Improved Phase-Locked Loop Circuits
[ETRI] ETRI Journal
2008 .04
-
CCD 이미지 센서용 AFE를 위한 Variable-Multiplying D/A Converter (V-MDAC)
대한전자공학회 학술대회
2007 .05
-
Design and Characterization of a 10 Gb/s Clock and Data Recovery Circuit Implemented with Phase-Locked Loop
[ETRI] ETRI Journal
1999 .06
-
A Design of CMOS 1st-Order Delay-Line DPLL for Clock Regeneration
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
1996 .01
-
Stability and Performance Investigations of Model Predictive Controlled Active-Front-End (AFE) Rectifiers for Energy Storage Systems
JOURNAL OF POWER ELECTRONICS
2015 .01
-
Phase Difference Measure를 통한 1㎐ Sync Enhancement 구조 설계
한국항공우주학회 학술발표회 초록집
2000 .11
-
One Chip Implementation of LL-DPLL Type Clock Recovery For Continuous and Burst Mode Coherent Satellite Demodulators
ICEIC : International Conference on Electronics, Informations and Communications
1995 .08
-
One Chip Implementation of LL-DPLL Type Clock Recovery for Continuous and Burst Mode Coherent Satellite Demodulators
ICEIC : International Conference on Electronics, Informations and Communications
1995 .01
-
위성방송용 QPSK 복조기를 위한 DPLL구조의 Carrier Recovery Loop 설계
대한전자공학회 학술대회
2001 .06
-
ECG와 PPG를 동시에 측정할 수 있는 바이오포텐셜 아날로그 프론트 엔드 (AFE)
대한전자공학회 학술대회
2016 .06
이 논문의 저자 정보
최근 본 자료
댓글(0)
0