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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.17 No.2
- 발행연도
- 2017.4
- 수록면
- 192 - 198 (7page)
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In this paper, we propose a novel double gate vertical channel tunneling field effect transistor (DVTFET) with a dielectric sidewall and optimization characteristics. The dielectric sidewall is applied to the gate region to reduced ambipolar voltage (V<SUB>amb</SUB>) and double gate structure is applied to improve on-current (I<SUB>ON</SUB>) and subthreshold swing (SS). We discussed the fin width (W<SUB>S</SUB>), body doping concentration, sidewall width (W<SUB>side</SUB>), drain and gate underlap distance (X<SUB>d</SUB>), source doping distance (X<SUB>S</SUB>) and pocket doping length (X<SUB>P</SUB>) of DVTFET. Each of device performance is investigated with various device parameter variations. To maximize device performance, we apply the optimum values obtained in the above discussion of a optimization simulation. The optimum results are steep SS of 32.6 mV/dec, high I<SUB>ON</SUB> of 1.2× 10<SUP>-3</SUP> A/ μ m and low V<SUB>amb</SUB> of -2.0 V.
목차
Abstract
I. INTRODUCTION
II. SIMULATION STRUCTURE
III. SIMULATION AND DISCUSSION
V. CONCLUSIONS
ACKNOWLEDGMENTS
REFERENCES
참고문헌 (16)
참고문헌 신청
K. K. Bhuwalka, S. Sedlmaier, A. Ludateck, C. Tolksdorf, J. Schulze, and I. Eisele, “Vertical tunnel field-effect transistor,” IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 279-282, Feb. 2004.
Pei-Yu Wang, and Bing-Yue Tsui, Experimental Demonstration of p-Channel Germanium Epitaxial Tunnel Layer (ETL) Tunnel FET With High Tunneling Current and High ON/OFF Ratio. IEEE Electron Device Letters, vol. 36, no. 12, pp.1264- 1266, Feb. 2015.
W. M. Reddick and G. A. J. Amaratunga, “Silicon surface tunnel transistor,” Appl. Phys. Lett., vol. 67, no. 4, pp. 494?496, Jul. 1995.
W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec,” IEEE Electron Device Lett, vol. 28, no. 8, pp. 743? 745, Aug. 2007.
J. H. Kim, S. W. Kim and H. W. Kim, “Vertical type double gate tunnelling FETs with thin tunnel barrier,” IET Electron. Lett., vol. 51, no. 9, pp. 718?720, Apr. 2015.
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UCI(KEPA) : I410-ECN-0101-2018-020-000839691