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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.16 No.2
- 발행연도
- 2016.4
- 수록면
- 172 - 178 (7page)
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초록· 키워드
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In this paper, we propose a sub-10 nm Ge/GaAs heterojunction-based tunneling field-effect transistor (TFET) with vertical band-to-band tunneling (BBT) operation for ultra-low-power (LP) applications. We design a stack structure that is based on the Ge/GaAs heterojunction to realize the vertical BBT operation. The use of vertical BBT operations in devices results in excellent subthreshold characteristics with a reduction in the drain-induced barrier thinning (DIBT) phenomenon. The proposed device with a channel length (Lch) of 5 nm exhibits outstanding LP performance with a subthreshold swing (S) of 29.1 mV/dec and an off-state current (Ioff) of 1.12 × 10<SUP>-11</SUP> A/μm. In addition, the use of the high-k spacer dielectric HfO₂ improves the on-state current (Ion) with an intrinsic delay time (τ) because of a higher fringing field. We demonstrate a sub-10 nm LP switching device that realizes a good S and lower Ioff at a lower supply voltage (VDD) of 0.2 V.
목차
Abstract
I. INTRODUCTION
II. DEVICE STRUCTURE AND DESIGN
III. RESULTS AND DISCUSSION
IV. CONCLUSIONS
REFERENCES
참고문헌 (16)
참고문헌 신청
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Z. X. Chen, H. Y. Yu, N. Singh, N. S. Shen, R. D. Sayanthan, G. Q. Lo, and D.-L. Kwong, “Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires,” IEEE Electron Device Lett., Vol. 30, No. 7, pp. 754-756, Jul., 2009.
R. Gandhi, Z. Chen, N. Singh, K. Banerjee, and S. Lee, “CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With ≤ 50-mV/decade Subthreshold Swing,” IEEE Electron Device Lett., Vol. 32, No. 11, pp. 1504-1506, Nov., 2011.
A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy-efficient electronic switches,” Nature, Vol. 479, No. 7373,, pp. 329-337, Nov., 2011.
Y. Morita, T. Mori, S. Migita, W. Mizubayashi, A. Tanabe, K. Fukuda, T. Masukawa, K. Endo, S. O’uchi, Y. X. Liu, M. Masahara, and H. Ota, “Performance Enhancement of Tunnel Field-Effect Transistors by synthetic Electric Field Effect,” IEEE Electron Device Lett., Vol. 35, No. 7, pp. 792-794, Jul., 2014.
Z. X. Chen, H. Y. Yu, N. Singh, N. S. Shen, R. D. Sayanthan, G. Q. Lo, and D.-L. Kwong, “Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires,” IEEE Electron Device Lett., Vol. 30, No. 7, pp. 754-756, Jul., 2009.
R. Gandhi, Z. Chen, N. Singh, K. Banerjee, and S. Lee, “CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With ≤ 50-mV/decade Subthreshold Swing,” IEEE Electron Device Lett., Vol. 32, No. 11, pp. 1504-1506, Nov., 2011.
A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy-efficient electronic switches,” Nature, Vol. 479, No. 7373,, pp. 329-337, Nov., 2011.
Y. Morita, T. Mori, S. Migita, W. Mizubayashi, A. Tanabe, K. Fukuda, T. Masukawa, K. Endo, S. O’uchi, Y. X. Liu, M. Masahara, and H. Ota, “Performance Enhancement of Tunnel Field-Effect Transistors by synthetic Electric Field Effect,” IEEE Electron Device Lett., Vol. 35, No. 7, pp. 792-794, Jul., 2014.
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