논리회로 상호간의 연결도 검증 ( Verification of Logic Gate Interconnection )

정자춘 ,  경종민

전자공학회논문지

1987 .03

New Dynamic Logic Gate Design Method for Improved TFT Circuit Performance

Jeong ,  Ju-Young ,  Kim 외 1명

Journal of information display

2005 .01

게이트 레벨 논리 검증 시스템 ( A Gate Level Logic Verification System )

최훈규 ,  김성수 ,  권용준 외 1명

대한전자공학회 학술대회

1987 .05

Design of Quaternary Logic gate Using Double Pass-transistor Logic with neuron MOS Threshold gate

Soo Jin Pa ,  k ,  Byoung Hee Yoon 외 1명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2003 .07

LOGIC-CHECKER : A CORRECTING FUNCTION FOR GATE ERRORS IN LOGIC SIMULATION AND ITS IMPLEMENTATION

Satoshi Wakabayashi ,  Hi ,  oyuki Ishikawa 외 1명

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1989 .01

Comparative Study on the Structural Dependence of Logic Gate Delays in Double-Gate and Triple-Gate FinFETs

Kwan Young Kim ,  Jae Man Jang ,  Dae Youn Yun 외 2명

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE

2010 .06

Design of a Complementary Pass Gate Network for a Multiple-Valued Logic System

Kyu Ik Sohng ,  Kazuhi ,  o Ho 외 3명

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1987 .01

A Rule-Based System for VLSI Gate-level Logic Optimization

Seong Bong Lee ,  Jong Hwa Chong

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1988 .01

A Logic Verification ＆ Synthesis System ( I ) ( A Logic Verification and Synthesis System ( 1 ) )

조중휘 ,  이성봉 ,  박성범 외 1명

대한전자공학회 학술대회

1985 .01

New Logic Simulation by the Gate-Level Waveform Relaxation Method

Ki Jun Lee

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1988 .01

Junctionless Sandwiched-gate Logic Design using Novel Device Structure

Myunghwan Ryu ,  Youngmin Kim

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE

2018 .08

A Universal Gate for Combinational Design of QCA Circuits

Young Bok Kim ,  Yong-Bin Kim ,  F. Lomba 외 1명

대한전자공학회 ISOCC

2009 .11

Logic Simulation

권태욱

대한전자공학회 단기강좌

1983 .01

SEA-OF-GATES

김진구

CAD기술특강

1989 .01

2-bit/Cell Split Gate Flash Memory with Double Gate

2-bit/Cell Split Gate Flash Memo ,  y with Double Gat ,  Il Han Pa 외 5명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2007 .07

Gate Array

오용협

전자공학회지

1992 .06

게이트 · 레벨 논리 시뮬레이션 ( Gate Level Logic Simulation )

고성원 ,  박성범 ,  정정화

대한전자공학회 학술대회

1984 .01

확장논리에 기초한 순차디지털논리시스템 및 컴퓨터구조에 관한 연구

박춘명

한국인터넷방송통신학회 논문지

2008 .01

3-Level Gate Drive Design

노재석 ,  배기훈 ,  강호현 외 1명

전력전자학회 학술대회 논문집

2018 .07

STUDIES ON FABRICATION TECHNIQUES OF SUB-0.4μm T-GATE AND Γ-GATE STRUCTURES USING UV LITHOGRAPHY

Il Hyeong Lee ,  Sung Soo Kim ,  Yeon Sik Chae 외 2명

ICVC : International Conference on VLSI and CAD

1995 .01