Feedback 효과를 고려한 Waveform Relaxation 방식에 의한 Timing Simulation ( A Timing Simulation with Waveform Relaxation-Considering the Feedback Effect )

전영현 ,  이창우 ,  박송배 외 1명

대한전자공학회 학술대회

1986 .01

Waveform Relaxation 과 Event Driven 기법을 이용한 Timing Simulation ( A New Event Driven Timing Simulation Based on Waveform Relaxation Method )

김택수 ,  조대형 ,  천명근 외 1명

대한전자공학회 학술대회

1987 .05

Feedback 효과를 고려한 Waveform Relaxation 방식에 의한 Timing Simulation

전영형 ,  이창우 ,  이기준 외 1명

대한전자공학회 학술대회

1986 .06

Numerical Stability and Multirate Effect in Waveform Relaxation Algorithm with Under Relaxation Technique

Koichi Hayashi ,  Hideki Asai

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1991 .01

Logic Simulation

권태욱

대한전자공학회 단기강좌

1983 .01

Timing Simulator by Waveform Relaxation Considering the Feedback Effect

Y. H. Jun ,  C. W. Lee ,  K. J. Lee 외 2명

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1986 .01

Circuit and Electromagnetic Hybrid Simulation Technique Based on Waveform Relaxation Method

Masaki Unno ,  Hideki Asai

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2009 .07

A Waveform Relaxation Method Applicable to Bipolar Digital Circuits

Mikio Nakano ,  Youichi ,  ou Mae 외 2명

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1990 .01

New Dynamic Logic Gate Design Method for Improved TFT Circuit Performance

Jeong ,  Ju-Young ,  Kim 외 1명

Journal of information display

2005 .01

Logic Gate간의 상호 연결도 검증 ( Verification of Logic Gate Interconnectivity )

정자춘 ,  경종민

대한전자공학회 학술대회

1985 .01

On the Consideration of Waveform Relaxation Method for Circuits with Lossless Transmission Lines

Ryuichi Mu ,  ayama ,  Nozomu Hamada

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1987 .01

LOGIC-CHECKER : A CORRECTING FUNCTION FOR GATE ERRORS IN LOGIC SIMULATION AND ITS IMPLEMENTATION

Satoshi Wakabayashi ,  Hi ,  oyuki Ishikawa 외 1명

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1989 .01

모듈 수준 클록 게이팅을 위한 시뮬레이션 웨이브폼 분석 기법

김제선 ,  김영훈 ,  이혁재

대한전자공학회 학술대회

2010 .06

게이트 · 레벨 논리 시뮬레이션 ( Gate Level Logic Simulation )

고성원 ,  박성범 ,  정정화

대한전자공학회 학술대회

1984 .01

Parallel Circuit Simulation Based on a Relaxation Method

Tetsuo Kaga ,  Junnichi Niitsuma ,  Fumuyo Kawafuji

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1995 .01

Acceleration of a Schwarz Waveform Relaxation Method for Parabolic Problems.

M. Ca ,  bey

한국전산유체공학회 학술대회논문집

2006 .05

Design of Quaternary Logic gate Using Double Pass-transistor Logic with neuron MOS Threshold gate

Soo Jin Pa ,  k ,  Byoung Hee Yoon 외 1명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2003 .07

A Rule-Based System for VLSI Gate-level Logic Optimization

Seong Bong Lee ,  Jong Hwa Chong

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1988 .01

Relaxation Times Calculated from the Relaxation Function

Hoo Sung Lee

한국고분자학회 학술대회 연구논문 초록집

1986 .10

Dynamically Overlapped Partitioning Technique to Implement Waveform Relaxation Simulation of Bipolar Circuits

Bandi Vijaya Gopal ,  Hideki Asai

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1993 .01