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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2008.11
- 수록면
- 395 - 398 (4page)
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초록· 키워드
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Coarse-grained reconfigurable architecture is good for both performance and flexibility. However, it is not easy to map applications to such architecture since it requires compilation of the application and configuration of the architecture at the same time while trying to maximally exploit the parallelism in the application and the architecture. In this paper, we introduce an approach to mapping applications to coarse-grained reconfigurable architecture based on high-level synthesis techniques. We adopt performance enhancing techniques including loop unrolling and loop pipelining for temporal mapping on a reconfigurable array architecture. Experimental results with DSPstone benchmark examples show the effectiveness of the proposed approach.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. TARGET ARCHITECTURE
Ⅲ. MAPPING ALGORITHM
Ⅳ. EXPERIMENTAL RESULT
Ⅴ. CONCLUSION
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001759096