지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2010.11
- 수록면
- 95 - 98 (4page)
이용수
초록· 키워드
오류제보하기
The coarse-grained reconfigurable image stream processor (CRISP) architecture is introduced for the image processing demands of high-definition (HD) cameras and camcorders. With several architectural concepts of the reconfigurable architecture, the CRISP architecture is proposed to meet the performance and flexibility requirements of the HD cameras. A multi-frame processing system with CRISP is implemented to achieve the real-time HD video recording and 11M-pixel image processing capability. Compared with the performance of the high-dynamic-range image fusion algorithm implemented with a general-purpose processor, 106 times speed-up is achieved by the proposed processor with high image quality of 42.5dB in PSNR.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. CRISP ARCHITECTURAL CONCEPT
Ⅲ. PROPOSED PROCESSOR ARCHITECTURE
Ⅳ. MULTI-FRAME PROCESSING
Ⅴ. CONCLUSION
REFERENCES
참고문헌 (0)
참고문헌 신청함께 읽어보면 좋을 논문
논문 유사도에 따라 DBpia 가 추천하는 논문입니다. 함께 보면 좋을 연관 논문을 확인해보세요!
-
Automatic Mapping of Application to Coarse-Grained Reconfigurable Architecture based on High-Level Synthesis Techniques
대한전자공학회 ISOCC
2008 .11
-
Chip Implementation of a Coarse-Grained Reconfigurable Architecture Supporting Floating-Point Operations
대한전자공학회 ISOCC
2008 .11
-
Reconfigurable Co-synthesis System Architecture
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2005 .07
-
High Performance, Low Power Reconfigurable Processor for Embedded Systems
대한전자공학회 ISOCC
2007 .10
-
A Fast SIFT Implementation Based on Integer Gaussian and Reconfigurable Processor
한국정보전자통신기술학회 논문지
2009 .09
-
Design of Reconfigurable Array-Processor based Crypto Chip
대한전자공학회 학술대회
2017 .01
-
Design and Evaluation of a Coarse-Grained Reconfigurable Architecture
대한전자공학회 ISOCC
2004 .10
-
Design Consideration for Reconfigurable Processor DS-HIE : Trade-off between Performance and Chip Area
대한전자공학회 ISOCC
2011 .11
-
ARCHITECTURE OF GENERAL PURPOSE RECONFIGURABLE LOGIC CELL
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2006 .07
-
A Dynamic Reconfigurable Processor and a Design Tool for the Next Generation ECUs
대한전자공학회 ISOCC
2009 .11
-
An Implementation of Video Streaming Processing on a Dynamically Self-Reconfigurable System
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2005 .07
-
An Approach for Area-Efficient Coarse-Grained Reconfigurable Architecture Dedicated to Media Processing
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2005 .07
-
Chip Implementation of a Coarse-Grained Reconfigurable Architecture
대한전자공학회 ISOCC
2006 .10
-
랜덤 연결 구조를 갖는 재구성형 프로세서의 성능 분석
대한전자공학회 학술대회
2010 .11
-
Design of SIMT Architecture-based Reconfigurable Image Signal Processor
INTERNATIONAL CONFERENCE ON FUTURE INFORMATION & COMMUNICATION ENGINEERING
2015 .06
-
AN FPGA IMPLEMENTATION OF PARTIAL DYNAMIC RECONFIGURATION CONTROLLERS AND PROCESSOR INTERFACES FOR A PROCESSOR-BASED SYSTEM WITH RECONFIGURABLE LOGICS
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2006 .07
-
Performance Evaluation of a Reconfigurable Instruction Set Processor
대한전자공학회 ISOCC
2008 .11
-
Automated Architecture Exploration for Low Energy Reconfigurable AGU
대한전자공학회 ISOCC
2011 .11
-
재구성 가능한 신경망 프로세서의 설계
대한전자공학회 학술대회
1999 .11
-
HD-RESOLUTION DEPTH IMAGE GENERATION SYSTEM USING SINGLE TOF CAMERA AND STEREO HD CAMERAS
한국멀티미디어학회 국제학술대회
2011 .07
이 논문의 저자 정보
최근 본 자료
댓글(0)
0
UCI(KEPA) : I410-ECN-0101-2013-569-001489028