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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2008.11
- 수록면
- 330 - 333 (4page)
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A new scheduling method considering bit level delays for high level synthesis is proposed. Conventional bit level delay computation for high-level synthesis was usually limited for specific resources. However, we have developed an efficient bit level delay computation method which is applicable to various resources, in this research. This method is applied to scheduling. The scheduling algorithm is based on list scheduling and executes chaining considering bit level delays. Furthermore, multicycle chaining can be allowed to improve performance under resource constraints. Experimental results on several well-known DSP examples show that our method improves the performance of the results by 14.7% on the average.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. CHAINING BASED ON BIT LEVEL DELAY
Ⅲ. BIT LEVEL DELAY COMPUTATION
Ⅳ. SCHEDULING ALGORITHM
Ⅴ. EXPERIMENTAL RESULTS
Ⅵ. CONCLUSIONS
ACKNOWLEDGMENT
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001758933