지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2008.11
- 수록면
- 314 - 317 (4page)
이용수
초록· 키워드
오류제보하기
In this paper a novel approach is proposed for the implementation of asynchronous pipelined circuits. In this approach, Synchronous FPGAs form Xilinx and Altera are used for implementing the asynchronous pipelined Circuits using two phase bundled data protocol. Asynchronous pipelined circuits have many potential advantages over their synchronous equivalents including lower latency, lower power consumption, high throughput, avoiding clock skew problem, etc., In this proposed approach, Muller C-element is used to generate the control signals in the handshaking circuit and Double Edge Triggered D-flip-flop (DETDFF) is used to ensure the two phase operation of the control signal generation. To verify the efficacy of this approach, an asynchronous pipelined 4 state, 1/2-rate viterbi decoder is implemented on Cyclone Ⅱ FPGA using Quartus Ⅱ Altera tool. The throughput of asynchronous pipelined Viterbi decoder using the proposed approach is 181Mbps which is 2.83 times greater than that of the synchronously pipelined Viterbi decoder with 35% increase in area.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. VITERBI ALGORITHM
Ⅲ. ASYNCHRONOUS PIPELINING
Ⅳ. PROPOSED ASYNCHRONOUS VITERBI DECODER
Ⅴ IMPLEMENTATION RESULTS
Ⅵ CONCLUSION
REFERENCES
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