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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2008.11
- 수록면
- 188 - 191 (4page)
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Employing a small L0-cache between an MPU core and an L1-cache is one of the most promising approaches for reducing the energy consumption of memory subsystems. Since the L0-cache is small, if there is a hit, the energy consumption will be reduced. On the other hand, if there is a miss, one extra cycle is required to access the L1-cache. This leads to a degradation of the processor performance. For resolving this problem, a Single cycle accessible Two-level Cache (STC) architecture is proposed in this paper. This architecture makes it possible to access to both the L0 and the L1 caches from an MPU core in a cycle. Experiments using several benchmark programs demonstrate that the STC architecture reduces the energy consumption of memory subsystems by 13% without any performance degradation compared to the best results obtained by previous approaches.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. RELATED WORK
Ⅲ. MOTIVATION AND OUR APPROACH
Ⅳ. STC ARCHITECTURE
Ⅴ. EXPERIMENTAL RESULTS
Ⅵ. CONCLUSIONS
ACKNOWLEDGMENT
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001758599