지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2009.11
- 수록면
- 573 - 576 (4page)
이용수
초록· 키워드
오류제보하기
In this paper, we introduce 3D graphics cache system to increase memory utilization and solve a memory bottleneck problem for an embedded system. We propose a novel pixel cache and a texture cache for a mobile 3D graphics hardware accelerator. The pixel cache enhances rendering performance by adopting a new write back algorithm and the texture cache also enhances the performance by adopting a multi-level, multi-port and non-blocking architecture. And all caches are optimized for AMBA3.0 AXI on-chip bus protocol. Also the proposed cache architecture can alleviate the memory bottleneck problem by preventing intensive memory accesses and improving cache efficiency by implementing novel cache architectures and multiple outstanding transactions. Also we can reduce a peak power which is a critical problem for an embedded system. We have evaluated the new proposed caches on 3D graphics IP on a SOC environment in where various IPs are embedded. The simulation results show the effectiveness of the proposed methods.
목차
Abstract
I. INTRODUCTION
II. PROPOSED METHOD
III. IMPLEMENTATION
IV. EXPERIMENTS
V. CONCLUSION
References
참고문헌 (0)
참고문헌 신청함께 읽어보면 좋을 논문
논문 유사도에 따라 DBpia 가 추천하는 논문입니다. 함께 보면 좋을 연관 논문을 확인해보세요!
-
A study on the Efficiency Cache Model based on the Embedded Systems
INTERNATIONAL CONFERENCE ON FUTURE INFORMATION & COMMUNICATION ENGINEERING
2014 .06
-
A Study on Constructing the Embedded Systems based on Higher value
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2007 .07
-
An adaptive write back method for on chip cache
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2009 .07
-
An auto-resize cache structure for high-performance and low-power
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2009 .07
-
A New Hybrid Architecture for Cooperative Web Caching
JUCT : Journal of Ubiquitous Convergence Technology
2008 .05
-
선택적 캐시 플러시를 위한 캐시 구현
대한전자공학회 학술대회
2015 .11
-
Memory Management Unit 및 Cache System의 설계 ( Memory Management Unit and Cache System Design )
대한전자공학회 기타 간행물
1992 .01
-
Preventing Fast Wear-out of Flash Cache with An Admission Control Policy
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2015 .10
-
Dynamic Probabilistic Caching Algorithm with Content Priorities for Content-Centric Networks
[ETRI] ETRI Journal
2017 .10
-
누전 에너지 관리를 고려한 공유 캐시 파티션 정책
대한전자공학회 학술대회
2007 .11
-
The Design of Cache Architecture in 32-bit RISC for the Performance Improvement
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2007 .07
-
Selective Access to the Instruction Cache for Low-Power Embedded Systems
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2007 .07
-
A Single Cycle Accessible Two-Level Cache Architecture for Reducing the Energy Consumption of Embedded Systems
대한전자공학회 ISOCC
2008 .11
-
다양한 cache block 크기에 의한 시스템의 성능 변화
대한전자공학회 학술대회
2003 .07
-
Performance and Energy-Efficiency Analysis of Hybrid Cache Memory based on SRAM-MRAM
대한전자공학회 ISOCC
2012 .11
이 논문의 저자 정보
최근 본 자료
댓글(0)
0
UCI(KEPA) : I410-ECN-0101-2013-569-001483526