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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications ITC-CSCC : 2009
- 발행연도
- 2009.7
- 수록면
- 822 - 825 (4page)
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초록· 키워드
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In this paper, we design a cache scheme which can reduce the power consumption and increase the performance of cache through auto-resize of L1 cache, which is called auto-selecting cache scheme. Cache memory occupies a significant fraction of a chip’s overall power consumption. Recent researches advocate using “resizable” to adjust cache capability based on the fact that requirement in applications will reduce cache size and power consumption. Based on the fact that different programs need different sizes of instruction and data cache, an auto-selecting cache scheme is proposed. This scheme can dynamically adjust the sizes of level 1 cache according to program requirement of instruction and data cache. The proposed structure can reduce power consumption and improve cache performance. According to the SPEC2000 simulation, the average power consumption of L1 cache is reduced by 7.43% and the average of energy delay production is improved by 16.08% with auto-selecting cache structure compared traditional one.
목차
Abstract
1. Introduction
2. Approach
3. Simulation result
4. Conclusions
5. References
6. ACKNOWLEDGMENT
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UCI(KEPA) : I410-ECN-0101-2012-569-004021833