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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications ITC-CSCC : 2008
- 발행연도
- 2008.7
- 수록면
- 1,105 - 1,108 (4page)
이용수
초록· 키워드
오류제보하기
In this paper, we propose an area-efficient VLSI architecture of H.264/AVC CAVLC decoder. In the proposed architecture, we reduce the decoder area by rearranging the lookup tables. We also save the bus area and cycles by delaying T1s decoding to the final reordering step which is performed in output buffer. To remove the overlapped logics we combine a controller and a barrel shifter. By using the proposed architecture, we can reduce the area by about 30% compared with previous work. We design the proposed decoder using Verilog HDL and synthesize using 0.35??m standard cell library. We verify the proposed architecture by simualation that the designed decoder can run at the frequency of 50Mhz.
목차
Abstract
1. Introduction
2. Algorithm and Previous works
3. Proposed CAVLC decoder architecture
4. Verification and Performance Comparison
5. Conclusion
References
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