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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2010.11
- 수록면
- 182 - 185 (4page)
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This paper presents the power-performance trade off of three different cache compression algorithms. Cache compression improves
performance, since the compressed data increases the effective cache capacity by reducing the cache misses. The unused memory cells
can be put into sleep mode to save static power. The increased performance and saved power due to cache compression must be more than the delay and power consumption added due to CODEC(COmpressor and DECompressor) block respectively. Among the studied algorithms, power-delay characteristic of Frequent Pattern compression(FPC) is found to be the most suitable for cache compression.
performance, since the compressed data increases the effective cache capacity by reducing the cache misses. The unused memory cells
can be put into sleep mode to save static power. The increased performance and saved power due to cache compression must be more than the delay and power consumption added due to CODEC(COmpressor and DECompressor) block respectively. Among the studied algorithms, power-delay characteristic of Frequent Pattern compression(FPC) is found to be the most suitable for cache compression.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. REVIEW OF THE COMPRESSION ALGORITHMS
Ⅲ. COMPARISION OF COMPRESSION PERFORMANCE OF ALGORITHMS
Ⅳ. HARWARE IMPLEMENTATION OF COMPRESSION SCHEME
Ⅴ. SIMULATION RESULTS AND ANALYSIS
Ⅵ. CONCLUSIONS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001489240