Partial Scan Design Based on Levelized Combinational Structure

Sung-Ju Pa ,  k

Journal of Electrical Engineering and Information Science

1997 .06

완전한 조합회로화에 의한 부분 스캔 설계 ( Partial Scan Design Based on the Levelized Combinational Structure )

박성주 ,  김루진 ,  박종욱

대한전자공학회 학술대회

1996 .07

효율적인 Partial Scan 설계 알고리듬

金倫弘 ,  新載興

전기학회논문지 P

2004 .12

Master-Slave 기법을 적용한 System Operation의 동작 검증

金吝洙 ,  閔炯福

전기학회논문지

2009 .01

Output Signal Probability from a Combinational Circuit

Byung Ho Jo ,  Hee Yeung Hwang

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1990 .01

On the Correction of Multiple Design Errors in Combinational Logic Circuits

I ,  ith Pome ,  anz 외 2명

ICVC : International Conference on VLSI and CAD

1993 .01

Design of Combinational Logic Switching Function using Array Graph

Chun-Myoung Pa ,  k

INTERNATIONAL CONFERENCE ON FUTURE INFORMATION & COMMUNICATION ENGINEERING

2012 .06

Labeling Scheme for Fault Simulation of Combinational Circuits

Han Heung Kim ,  S. H. Hwang ,  Chong Min Kyung

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1991 .01

A Probabilistic Model of Levelized Cost of Electricity(LCOE) for Korean Offshore Wind

Kihwan Kim ,  Duk Oh Lim ,  Gil-Lim Yoon

AFORE

2019 .11

SAT-Based Combinational Equivalence Checking with Don’t Care

Myoung-Jin Nam ,  Chang-Hun Sung ,  Jin-Young Choi

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2004 .07

Combinational Logic Optimization for a Hardware based HEVC Transform

Anish Tamse ,  Hyuk Jae Lee ,  Chae Eun Rhee

한국방송미디어공학회 학술발표대회 논문집

2014 .11

Rule-Base를 이용한 조합논리 최적화 시스템 ( Combinational Logic Optimization System Based on Rule-Base )

김원응 ,  최병윤 ,  양인환 외 2명

한국통신학회 학술대회논문집

1988 .01

Oil-encapsulating Core-shell Structured Nanoparticles for Combinational Cancer Therapy

오미화 ,  김지선 ,  이정유 외 1명

한국고분자학회 학술대회 연구논문 초록집

2011 .10

A Partial Scan Test Method without the Data Holding Overhead

Dong Ho Lee ,  Hyun Chul Noh

ICVC : International Conference on VLSI and CAD

1997 .01

유사조합 회로로의 변환에 기초한 부분 스캔 기법을 이용한 디지탈 순차 회로의 테스트 기법 연구

閔炯福

전기학회논문지

1994 .03

조합논리회로의 결합검출 ( Fault Detection in Combinational Circuits )

고경식 ,  허웅

전자공학회지

1974 .11

A Study of Cooling Schemes for the Generation of Input Pairs of CMOS Combinational Circuits Using the Simulated Annealing Algorithm

Albe ,  to Palacios Pawlovsky ,  Hi 외 1명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2005 .07

간헐적 신재생에너지의 수용 한계를 고려한 전력계통의 비용 분석

김두천 ,  박중구

한국에너지학회 학술발표회

2017 .09

Multiple-Output Value Array Graphs Based Algorithms for Multiple-Valued Combinational Logic Function Manipulation

Byoung Hee Yoon ,  Jin Young O ,  Jong Hak Hwang 외 4명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

1998 .01