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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 1977.12
- 수록면
- 51 - 58 (8page)
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이 논문의 연구 히스토리 (6)
1981
1978
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초록· 키워드
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In this paper, an algorithm for generating the test set to detect all multiple stuck-at-faults in multiple-output combinational logic network is presented.
The algorithm represented here is the procedure to generate the test patterns by following steps;
First, the circuits constituted with the overlapped paths in the multiple output circuit are conception ally considered as lines and it is the pseudo-input lines of the multiple output circuit.
Next, the test patterns of the overlapped-path circuits and those of the output circuits contained the overlapped-path circuits are generated.
The Algorithm is derived from the conception of pseudo inputs by using the cause-effect equation.
And it is shown that the test patterns can be generated by simpler procedure than other methods and the procedure of generating minimum test patterns is derived.
The algorithm represented here is the procedure to generate the test patterns by following steps;
First, the circuits constituted with the overlapped paths in the multiple output circuit are conception ally considered as lines and it is the pseudo-input lines of the multiple output circuit.
Next, the test patterns of the overlapped-path circuits and those of the output circuits contained the overlapped-path circuits are generated.
The Algorithm is derived from the conception of pseudo inputs by using the cause-effect equation.
And it is shown that the test patterns can be generated by simpler procedure than other methods and the procedure of generating minimum test patterns is derived.
목차
ABSTRACT
Ⅰ. 序論
Ⅱ. 基本定義와 Test pattern 生成
Ⅲ. 最小 Test pattern生成
Ⅳ. 結論
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