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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE JOUNAL OF SEMICONDUCTOR THCHNOLOGY AND SCIENCE Vol.4 No.3
- 발행연도
- 2004.9
- 수록면
- 228 - 239 (12page)
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초록· 키워드
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In this paper, an analytical model accounting for the quantum effect. in MOSFETs has been developed to study the behaviour of high-k dielectric. and to calculate the threshold voltage of the device considering two dielectrics gate stack. The effect of variation in gate stack thickness and permittivity on surface potential, inversion layer charge density, threshold voltage, and In-Vo characteristics have also been studied. This work aims at presenting a relation between the physical gate dielectric thickness, dielectric constant and substrate doping concentration to achie"e targeted threshold voltage, together with minimizing the effect of gate tunneling current. The results so obtained are compared with the available simulated data and the other models available in the literature and show good agreement.
Index Terms-Quantization effects (QEs), Triangular Potential Well (TPW), Gate stack, Equivalent oxide thickness (EOT)
Index Terms-Quantization effects (QEs), Triangular Potential Well (TPW), Gate stack, Equivalent oxide thickness (EOT)
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. QUANTUM INVERSION SPACE CHARGE DENSITY
Ⅲ. SURFACE POTENTIAL BASED MODEL
Ⅳ. INTRODUCTION OF HIGH-K GATE DIELECTRICS
Ⅴ. RESULTS AND DISCUSSION
Ⅵ. CONCLUSION
ACKNOWLEDGMENT
APPENDIX A
REFERENCES
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