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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 한국과학기술원 정보전자연구소 IDEC Journal of Integrated Circuits and Systems IDEC Journal of Integrated Circuits and Systems Vol.7 No.4
- 발행연도
- 2021.10
- 수록면
- 39 - 43 (5page)
- DOI
- 10.23075/jicas.2021.7.4.008
이용수
초록· 키워드
오류제보하기
The industry has increased the word line (WL) layer to improve the density of 3D NAND flash. As the WL layer increases, the energy consumed to generate the boosted WL voltage has also increased. In 3D NAND flash, understanding the block configuration and operation of a word line driver (WL driver) with high energy consumption should be preceded to implement a 3D NAND flash with low energy consumption.
This study presents a conventional WL driver for triple-level cell 3D NAND flash to understand the operation and classify energy consumption. The conventional WL driver for a 56-WL layer is fabricated in 180nm UHV process, and it consumes 141.15nJ from a 2.2V during 1 unit of program pulse and verify period.
목차
등록된 정보가 없습니다.
참고문헌 (7)
참고문헌 신청
Hwang Huh / 2020 / A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique / 2020 IEEE International Solid - State Circuits Conference - (ISSCC) :220~221
Jae-Woo Park / 2021 / A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture / 2021 IEEE International Solid - State Circuits Conference - (ISSCC) :422~423
Ki-Tae Park / 2015 / Three-Dimensional 128 Gb MLC Vertical NAND Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming / IEEE Journal of Solid-State Circuits - (JSSC) 50(1):204~213
Sam-Kyu Won / 2011 / High-voltage word line generator for low-power program operation in NAND flash memories / IEEE Asian Solid-State Circuits Conference 2011 - (ASSCC) :169~172
Jong Hak Yuh / 2012 / Techniques for the fast settling of word lines in NAND flash memory / US Patent App. 20120075931, SANDISK TECHNOLOGIES, Inc
Jae-Woo Park / 2021 / A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture / 2021 IEEE International Solid - State Circuits Conference - (ISSCC) :422~423
Ki-Tae Park / 2015 / Three-Dimensional 128 Gb MLC Vertical NAND Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming / IEEE Journal of Solid-State Circuits - (JSSC) 50(1):204~213
Sam-Kyu Won / 2011 / High-voltage word line generator for low-power program operation in NAND flash memories / IEEE Asian Solid-State Circuits Conference 2011 - (ASSCC) :169~172
Jong Hak Yuh / 2012 / Techniques for the fast settling of word lines in NAND flash memory / US Patent App. 20120075931, SANDISK TECHNOLOGIES, Inc
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