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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 한국전기전자재료학회 Transactions on Electrical and Electronic Materials Transactions on Electrical and Electronic Materials 제22권 제4호
- 발행연도
- 2021.8
- 수록면
- 489 - 501 (13page)
- DOI
- https://doi.org/10.1007/s42341-020-00256-2
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This article is about an elaborative description of two dimensional investigative mathematical structure of fully depleted graded channel (GC) dual-material-double-gate (DMDG) silicon-on-insulator metal?oxide?semiconductor-fi eld-eff ecttransistor (SOI MOSFET). The surface potential contours in addition with electric field variation throughout the channel establish reduction of short-channel-effects (SCEs). To get better operational analysis, some new characteristics such as temperature effect and interface charge eff ects have been incorporated in the model. In this representation we also incorporate the consequences of high-k dielectric medium HfO2 instead of SiO2 and have made a comparison with the effect in various frameworks. In the GC DMDG composition, the surface potential as well as electric field throughout the channel shows close to step function variations which help to defeat the hot carrier along with drain-induced-barrier-lowering (DIBL) effects. As an outcome, the structure shows that the surface potential profi le increases by using GC DMDG structure over DMDG. All these outcomes of the proposed analytical representation have been compared by TCAD simulation consequence. Very good conformity is observed between them.
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참고문헌 (6)
참고문헌 신청
Ali A. Orouji / 2012 / Leakage current reduction in nanoscale fully-depleted SOI MOSFETs with modified current mechanism / Current Applied Physics 12(5):1366~1371
S. I. Garduño / 2011 / Contribution of the carrier tunneling and gate induced drain leakage eff ects to the gate and drain currents of fi n-shaped fi eld eff ect transistor / J. Appl. Phys 109(084524):1~7
A. Chaudhury / 2004 / Controlling short channel eff ects in deep submicron SOI MOSFETs for improved reliability : a review / IEEE. Trans. Devices. Mater Reliab 4(1):99~109
F. Balestra / 1987 / Double-gate silicon-on insulator transistor with volume inversion : a new device with greatly enhaced performance / IEEE. Electron. Device. Lett. EDL 8(9):410~412
N. P. Maity / 2019 / Comparative analysis of the quantum FinFET and trigate FinFET based on modeling and simulation / J. Comput. Electron 18(2):492~499
S. I. Garduño / 2011 / Contribution of the carrier tunneling and gate induced drain leakage eff ects to the gate and drain currents of fi n-shaped fi eld eff ect transistor / J. Appl. Phys 109(084524):1~7
A. Chaudhury / 2004 / Controlling short channel eff ects in deep submicron SOI MOSFETs for improved reliability : a review / IEEE. Trans. Devices. Mater Reliab 4(1):99~109
F. Balestra / 1987 / Double-gate silicon-on insulator transistor with volume inversion : a new device with greatly enhaced performance / IEEE. Electron. Device. Lett. EDL 8(9):410~412
N. P. Maity / 2019 / Comparative analysis of the quantum FinFET and trigate FinFET based on modeling and simulation / J. Comput. Electron 18(2):492~499
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