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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 한국전기전자재료학회 Transactions on Electrical and Electronic Materials Transactions on Electrical and Electronic Materials 제23권 제1호
- 발행연도
- 2022.2
- 수록면
- 45 - 51 (7page)
- DOI
- https://doi.org/10.1007/s42341-021-00316-1
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Surface passivation of n-type Crystalline Silicon wafer using thin dielectric films is an important and major factor in improving photovoltaic performance of HIT solar cells. In this study, Numerical simulation was carried out by using AFORS-HET simulation software in which energy band diagram with and without surface passivation (a-Si:H(i)) was investigated and the highest conduction band off set obtained on n type c-Si wafer is 0.85 eV which is comparatively higher than p-type c-Si wafer which was reported between 0.1 and 0.15 eV. Performance of HIT solar cell with passivation layer is simulated and obtained effi ciency of 12.9% by incorporating actual conditions to compare with experimentally obtained data. It has been understood that applying an eff ective dielectric passivation of silicon surface resulted with high open circuit voltage (Voc) and low surface recombination lead to an increase of cell efficiency by 1.1% (from 11.8 to 12.9%). Also, the simulated results shows that to obtain good conversion effi ciency Defect density of interface (Dit) should be lower than 1x10 11 cm ?2 eV ?1 . Validation of the simulation results is done by conducting PECVD experiments for optimizing the amorphous silicon passivation to a layer thickness down to 15 nm. HIT Solar cells have been developed, using the optimum layer of passivation, and their performance have been studied. An improvement in the minority charge carrier lifetime of ~53 μs (from 215 to 268 μs) and on the other hand reduction in the surface recombination velocity of ~ 12.9 cm/s (from 65.11 cm/s down to 52.23 cm/s) has been achieved through passivation which eff ectively increased the open circuit voltage (Voc) from 0.690 to 0.705 V. In this preliminary study, a conversion efficiency of 11.3% of heterojunction with intrinsic thin layer (HIT) solar cell on 10 mm × 10 mm n-c-Si wafer has been obtained.
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