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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.22 No.3
- 발행연도
- 2022.6
- 수록면
- 188 - 197 (10page)
- DOI
- 10.5573/JSTS.2022.22.3.188
이용수
초록· 키워드
오류제보하기
Recent research on NEM devices for logic and memory applications has been reviewed from the perspective of monolithic 3D (M3D) heterogeneous integration. In addition, the backgrounds of M3D CMOS-NEM reconfigurable logic (RL) circuits are described in detail. Moreover, 65-nm process based M3D CMOS-NEM RL circuits were proposed. It is predicted that proposed M3D CMOS-NEM RL circuits will exhibit 4.6x higher chip density, 2.3x higher operation frequency and 9.3x lower power consumption than CMOS-only ones (tri-state buffer case) for tile-to-tile operation.
목차
Abstract
I. INTRODUCTION
II. RESEARCH TRENDS OF NEM DEVICES
III. M3D CMOS-NEM RL CIRCUITS
IV. RESULTS AND DISCUSSION
V. CONCLUSION
REFERENCES
참고문헌 (23)
참고문헌 신청
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S. Chong, B. Lee, K. B. Parizi, J. Provine, S. Mitra, R. T. Howe and H.-S. P. Wong, “Integration of nanoelectromechanical (NEM) relays with silicon CMOS with functional CMOS-NEM circuit,” in Proc. Int. Electron Devices Meeting (IEDM), pp. 30.5.1-30.5.4, Dec. 2011.
W. Y. Choi and Y. J. Kim, “Three-dimensional integration of complementary metal-oxidesemiconductor-nanoelectromechanical hybrid reconfigurable circuits,” IEEE Electron Device Letters, vol. 36, no. 9, pp. 887-889, Sep. 2015.
J. L. Munoz-Gamarra, A. Uranga and N. Barniol, “CMOS-NEMS copper switches monolithically integrated using a 65 nm CMOS technology,” Micromachines, vol. 7, no. 2, Feb. 2016.
C. Chen, R. Parsa, N. Patil, S. Chong, K. Akarvardar, J. Provine, D. Lewis, J. Watt, R. T. Howe, H.-S. P. Wong and S. Mitra, “Efficient FPGAs using nanoelectromechanical relays,” in Proc. Int. Symp. on Field-Programmable Gate Arrays, pp. 273-282, Feb. 2010.
S. Chong, B. Lee, K. B. Parizi, J. Provine, S. Mitra, R. T. Howe and H.-S. P. Wong, “Integration of nanoelectromechanical (NEM) relays with silicon CMOS with functional CMOS-NEM circuit,” in Proc. Int. Electron Devices Meeting (IEDM), pp. 30.5.1-30.5.4, Dec. 2011.
W. Y. Choi and Y. J. Kim, “Three-dimensional integration of complementary metal-oxidesemiconductor-nanoelectromechanical hybrid reconfigurable circuits,” IEEE Electron Device Letters, vol. 36, no. 9, pp. 887-889, Sep. 2015.
J. L. Munoz-Gamarra, A. Uranga and N. Barniol, “CMOS-NEMS copper switches monolithically integrated using a 65 nm CMOS technology,” Micromachines, vol. 7, no. 2, Feb. 2016.
C. Chen, R. Parsa, N. Patil, S. Chong, K. Akarvardar, J. Provine, D. Lewis, J. Watt, R. T. Howe, H.-S. P. Wong and S. Mitra, “Efficient FPGAs using nanoelectromechanical relays,” in Proc. Int. Symp. on Field-Programmable Gate Arrays, pp. 273-282, Feb. 2010.
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