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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2022.6
- 수록면
- 33 - 38 (6page)
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Planner configuration thin film solar cells (TFSCs) with SnS/CdS heterojunction performed a lower short-circuit current (J<SUB>SC</SUB>). In this study, we have demonstrated a path to overcome deficiency in J<SUB>SC</SUB> by the incorporation of Se in the SnS absorber. We carried out the incorporation of Se in VTD grown SnS absorber by rapid thermal annealing (RTA). The diffusion of Se is mostly governed by RTA temperature (T<SUB>RTA</SUB>), also it is observed that film structure changes from cube-like to plate-like structure with T<SUB>RTA</SUB>. The maximum J<SUB>SC</SUB> of 23.1 mA cm<SUP>-2</SUP> was observed for 400°C with an open-circuit voltage (V<SUB>OC</SUB>) of 0.140 V for the same temperature. The highest performance of 2.21% with JSC of 18.6 mA cm<SUP>-2</SUP>, V<SUB>OC</SUB> of 0.290 V, and fill factor (FF) of 40.9% is observed for a T<SUB>RTA</SUB> of 300°C. In the end, we compare the device performance of Se- incorporated SnS absorber with pristine SnS absorber material, increment in J<SUB>SC</SUB> is approximately 80% while a loss in V<SUB>OC</SUB> of about 20% has been observed.
목차
ABSTRACT
1. Introduction
2. Experimental procedure
3. Result and discussion
4. Conclusion
References
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