지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.19 No.2
- 발행연도
- 2019.4
- 수록면
- 220 - 225 (6page)
- DOI
- 10.5573/JSTS.2019.19.2.220
이용수
초록· 키워드
오류제보하기
A DC-offset of a continuous-time linear equalizer (CTLE) is cancelled by an analog offset canceller (OFC). The bandwidth (BW) of the OFC is designed to be 10-㎑ not to affect the received signal integrity. The BW of the OFC set by an active-RC integrator is lowered by increasing the effective resistance through pulse width modulation (PWM). The input offset of the OFC itself is removed by employing chopping technique. The offset-cancelled CTLE is applied to a four-channel 12-Gb/s wireline receiver compliant with thehigh-definition multimedia interface (HDMI) version 2.1 standard. The 12-Gb/s wireline receiver has been implemented in a 28-㎚ CMOS process. The eye opening for the bit-error rate (BER) smaller than 10<SUP>-12</SUP> becomes larger than 0.26 unit-interval (UI) with the OFC while the BER is always larger than 10<SUP>-12</SUP> without the OFC.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. ARCHITECTURE AND IMPLEMENTATION
Ⅲ. EXPERIMENTAL RESULTS
Ⅳ. CONCLUSIONS
REFERENCES
참고문헌 (12)
참고문헌 신청
S. Gondi and B. Razavi, “Equalization and clock and data recovery techniques for 10-Gb/s CMOS serial-Link receivers,” IEEE J. Solid-State Circuits, Vol. 42, No. 9, pp. 1999-2011, Aug. 2007.
R. Payne, P. Landman, B. Bhakta, et al, “A 6.25- Gb/s binary transceiver in 0.13-μm CMOS for serial data transmission across high loss legacy backplane channels,” IEEE J. Solid-State Circuits, Vol. 40, No. 12, pp. 2646?2657, Dec. 2005.
S. Galal and B. Razavi, “10-Gb/s limiting amplifier and laser/modulator driver in 0.18-μm CMOS technology,” IEEE J. Solid-State Circuits, Vol. 38, No. 12, pp. 2138-2146, Dec. 2003.
E. A. Crain and M. H. Perrott, “A 3.125 Gb/s limit amplifier in CMOS with 42 dB gain and 1 μs offset compensation,” IEEE J. Solid-State Circuits, Vol. 41, No. 2, pp. 443-451, Jan. 2006.
J. E. Jaussi, G. Balamurugan, D. R. Johnson, et al, “8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew,” IEEE J. Solid-State Circuits, Vol. 40, No. 1, pp. 80?88, Jan. 2005.
R. Payne, P. Landman, B. Bhakta, et al, “A 6.25- Gb/s binary transceiver in 0.13-μm CMOS for serial data transmission across high loss legacy backplane channels,” IEEE J. Solid-State Circuits, Vol. 40, No. 12, pp. 2646?2657, Dec. 2005.
S. Galal and B. Razavi, “10-Gb/s limiting amplifier and laser/modulator driver in 0.18-μm CMOS technology,” IEEE J. Solid-State Circuits, Vol. 38, No. 12, pp. 2138-2146, Dec. 2003.
E. A. Crain and M. H. Perrott, “A 3.125 Gb/s limit amplifier in CMOS with 42 dB gain and 1 μs offset compensation,” IEEE J. Solid-State Circuits, Vol. 41, No. 2, pp. 443-451, Jan. 2006.
J. E. Jaussi, G. Balamurugan, D. R. Johnson, et al, “8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew,” IEEE J. Solid-State Circuits, Vol. 40, No. 1, pp. 80?88, Jan. 2005.
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