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논문 기본 정보

자료유형
학술저널
저자정보
Jin-ku Kim (Sogang University) Jong-bum Lim (Sogang University) Woo-cheol Cho (Sogang University) Kwang-Sik Shin (LG electronics) Hoshik Kim (LG Electronics) Hyuk-Jun Lee (Sogang University)
저널정보
대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.16 No.6
발행연도
2016.12
수록면
808 - 816 (9page)

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초록· 키워드

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As the number of CPU/GPU cores and IPs in SOC increases and applications require explosive memory bandwidth, simultaneously achieving good throughput and fairness in the memory system among interfering applications is very challenging. Recent works proposed priority-based thread scheduling and channel partitioning to improve throughput and fairness. However, combining these different approaches leads to performance and fairness degradation. In this paper, we analyze the problems incurred when combining priority-based scheduling and channel partitioning and propose dynamic priority thread scheduling and adaptive channel partitioning method. In addition, we propose dynamic address mapping to further optimize the proposed scheme. Combining proposed methods could enhance weighted speedup and fairness for memory intensive applications by 4.2% and 10.2% over TCM or by 19.7% and 19.9% over FR-FCFS on average whereas the proposed scheme requires space less than TCM by 8%.

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Abstract
Ⅰ. INTRODUCTION
Ⅱ. BACKGROUND
Ⅲ. PROPOSED SCHEME
Ⅳ. EXPERIMENTAL RESULTS
Ⅴ. CONCLUSIONS
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UCI(KEPA) : I410-ECN-0101-2017-569-001935058