지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2009.11
- 수록면
- 524 - 527 (4page)
이용수
초록· 키워드
오류제보하기
This paper proposes a low power spread spectrum clock generator (SSCG). The proposed SSCG is based on direct frequency synthesis and harmonic injection locking due to the highly digital frequency modulation and low power implementation. The prototype of the SSCG is implemented in 0.13 μm CMOS process. The proposed SSCG can generate 900 MHz spread spectrum signal with spread ratio of 1 %. The simulation results show that it has 35 dB EMI reduction and consumes 2.2 mW from 1.2 V supply.
목차
Abstract
I. INTRODUCTION
II. PROPOSED ARCHITECTURE
III. IMPLEMENTATION
IV. SIMULATION RESULTS
V. CONCLU
VI. ACKNOWLEDGEMENT
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001483400