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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ICEIC : International Conference on Electronics, Informations and Communications ICEIC : 2008
- 발행연도
- 2008.6
- 수록면
- 205 - 208 (4page)
이용수
초록· 키워드
오류제보하기
A novel level shifter for high speed and low power consumption using only p-channel low temperature poly-Si thin-film transistors (LTPS TFTs) is proposed. The circuitry only uses p-channel LTPS TFTs in system-on-panel has advantages of low cost and high yield. The proposed level shifter consists of four PTFTs, one capacitor and two signal lines. By using bootstrapping method through the capacitor, the speed of operation can be improved and the short circuit current can be reduced. Therefore, it has been achieved high speed and low power consumption without increasing the circuit area. By HSPICE simulation, we verified that the power consumption of the circuit is 378.4 ㎼ in 15㎒ with circuit dimension of 3195 ㎛² and the previously reported complementary cross-coupled type circuit consumes 1522 ㎼ at 15 ㎒ withcircuit dimension of 4130 ㎛².
목차
Abstract
1. Introduction
2. Previously reported level shifter
3. The proposed level shifter
4. Simulation results
5. Conclusions
References
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