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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- Korean Institute of Information Scientists and Engineers Journal of Electrical Engineering and Information Science Journal of Electrical Engineering and Information Science Vol.3 No.4
- 발행연도
- 1998.8
- 수록면
- 433 - 441 (9page)
이용수
초록· 키워드
오류제보하기
Performance prediction for digital designs has become more complex and cost-consuming as the circuit size increases. This paper is concerned with the circuit delay estimation at the gate level, which is one of the important factors in performance prediction. A delay model for digital CMOS circuits is proposed here, which can predict the delay efficiently and accurately for the wide range of input transition time, transistor size, and output load. This paper, first, constructs a delay model for the CMOS inverter, and then it is extended to other logic gates by converting the gate to an equivalent inverter. The performance of the model was compared with the SPICE simulation results to show how the model competes with SPICE in terms of efficiency and accuracy. Experimental results show that the proposed model has the accuracy of less than 5% relative error and is 70 times faster, compared with SPICE.
목차
Abstract
Ⅰ. Introduction
Ⅱ. Remodeling the Basic Characteristics
Ⅲ. Delay Model for Inverter
Ⅳ. Extension to Other Gates
Ⅴ. Comparison the Results with Simulation
Ⅵ. Conclusion
References
저자소개
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