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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- Korean Institute of Information Scientists and Engineers Journal of Electrical Engineering and Information Science Journal of Electrical Engineering and Information Science Vol.2 No.6
- 발행연도
- 1997.10
- 수록면
- 212 - 216 (5page)
이용수
초록· 키워드
오류제보하기
A new metal tip fabrication process for low voltage operation is reported in this paper. The key element of the fabrication process is that isotropic silicon etching and oxidation process used in silicon tip fabrication is utilized for gate hole size reduction and gate oxide layer. A metal FEA with 625 tips was fabricated in order to demonstrate the validity of the new process and submicron gate apertures were successfully obtained from originally 1.7㎛ diameter mask. The emission current above noise level was observed at the gate bias of 50V. The required gate voltage to obtain the anode current of 0.1㎂/tip was 74V and the emission current was stable above 2㎂/tip without any disruption. The local field conversion factor and the emitting area were calculated as 7.981×10^5㎝^(-1) and 3.2×10^(-14)㎠/tip, respectively.
목차
Abstract
Ⅰ. Introduction
Ⅱ. Fabrication
Ⅲ. Results and Discussion
Ⅳ. Conclusion
Acknowledgement
References
저자소개
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