단어인식 알고리즘의 병렬 처리를 위한 systolic 구조에 관한 연구 ( A Study on the Systolic Architecture for the Parallel Processing of Word Recognition Algorithms )

조남익 ,  이상욱 ,  김경태

대한전자공학회 학술대회

1987 .11

COMPUTER AIDED SYSTOLIC ARCHITECTURE DESIGN

I. Chang Jou ,  Tien So Shin

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1989 .01

Systolic Architecture in Signal Processing

이문기

대한전자공학회 단기강좌

1988 .01

A Systolic Array Architecture for Block Matching Algorithm

Jong Seob Baek ,  Seung Hyun Nam ,  Moon Key Lee

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1994 .01

A PARALLEL SYSTOLIC ARCHITECTURE OF REED-SOLOMON CODES

Jong Seob Baek ,  Young Shig Choi ,  Tae Geun Kim

ICVC : International Conference on VLSI and CAD

1995 .01

R-S 복호기의 Systolic 설계에 관한 연구 ( A Study on the Systolic Architecture of R-S Decoder )

박영만 ,  김창규 ,  이만영

대한전자공학회 학술대회

1988 .07

R-S 복호기의 Systolic 설계에 관한 연구

박영만 ,  김창규 ,  이만영

대한전기학회 학술대회 논문집

1988 .07

Parallel Processing in Architecture

박규호

대한전자공학회 단기강좌

1988 .01

Massively Parallel Processor based on Systolic Architecture for High-Performance Computation of Difference Schemes

Kenta ,  o Sano ,  Takano 외 3명

한국전산유체공학회 학술대회논문집

2006 .05

A Systolic Array Architecture for a Modular Multiplication Algorithm

Jung Tae Kim ,  Jong Wook Han ,  Hong Sub Lee

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1995 .01

An Effective Intra-Prediction Systolic Array Architecture

Su-Jin Lee ,  Cheong-Ghil Kim ,  Myoung-Seo Kim 외 1명

대한전자공학회 ISOCC

2004 .10

Pseudo-2축 제어 시스템 개발 ( Development of Pseudo-2 Axes Control System )

신승호 ,  강희준 ,  이흥희 외 2명

대한기계학회 춘추학술대회

1996 .01

Design Reconfigurable 2-D Systolic Array Using Pseudo Faulty Processing Element

Dong Suk Shin ,  Bong Jo Choo ,  Chong Ho Woo

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1995 .01

A High Speed Systolic VLSI Architecture for LZ Algorithm

Tae Young Lee ,  Seung Hyun Nam ,  Moon Key Lee 외 2명

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1995 .01

Bit-level Systolic Arrays for Genetic Algorithm

Myoung-Keun You ,  Jae-Jin Lee ,  Gi-Yong Song

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2005 .07

A Study on QR-RLS Algorithm with Systolic Array Architecture using CORDIC Algorithm

Moo Young Byun ,  Won Cheol Lee

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2005 .07

DCT ( Discrete Cosine Transform ) 의 병렬 연산을 위한 systolic 구조에 관한 연구 ( A Study on the Systolic Architecture for the Parallel Processing of Discrete Cosine Transform )

조남익 ,  이상욱

대한전자공학회 학술대회

1987 .11

Conservative Approximation–Based Full-Search Block Matching Algorithm Architecture for QCIF Digital Video Employing Systolic Array Architecture

Ganapathi Hegde ,  Am ,  itha K 외 3명

[ETRI] ETRI Journal

2015 .08

A Systematic Approach for Designing Fault Tolerant Systolic Architectures

M. O. Esonu ,  S. Ha ,  i 외 2명

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1989 .01

고속 신호 처리용 Systolic Array 설계 ( A High Speed Signal Processing Systolic Array Design )

신경욱 ,  최봉윤 ,  유종근 외 2명

한국통신학회 학술대회논문집

1985 .01