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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.24 No.3
- 발행연도
- 2024.6
- 수록면
- 226 - 239 (14page)
- DOI
- 10.5573/JSTS.2024.24.3.226
이용수
초록· 키워드
오류제보하기
Resistive random-access memory (RRAM) is a promising emerging non-volatile memory because it offers high density, low power, low cost, and large R-ratios (RHRS / RLRS). However, the sensing margin of RRAM is significantly degraded because of RRAM resistance variations and R-ratio degradation over usage. To overcome these challenges, this work proposes a reliable current sense amplifier assisted with dynamic reference (DR-CSA) to improve the sensing margin and robustness. The proposed sensing circuit detects a small voltage change through capacitive coupling and adjusts the reference current depending on the cell states (R<SUB>HRS</SUB>, R<SUB>LRS</SUB>) for sensing margin enhancement. It also reduces sensing delay and energy by up to 53% and 32%, respectively, compared with the conventional CSA. Also, the sensing speed is improved by 2.3x, 2.1x, and 1.9x compared to other current sensing schemes.
목차
Abstract
I. INTRODUCTION
II. REVIEW OF STATE-OF-THE-ART SENSE AMPLIFIERS
III. PROPOSED CURRENT SENSE AMPLIFIER WITH DYNAMIC REFERENCE(DR-CSA)
IV. SIMULATION RESULT AND COMPARISON
V. CONCLUSION
REFERENCES
참고문헌 (24)
참고문헌 신청
Khwa, W.-S., et al., “Emerging NVM circuit techniques and implementations for energy-efficient systems, in Beyond-CMOS Technologies for Next Generation Computer Design”. Springer, 2019, pp. 85-132.
Meena, J.S., et al., “Overview of emerging non-volatile memory technologies.” Nanoscale research letters, Sep. 2014, pp. 1-33.
Niu, D., et al. “Low power multi-level-cell resistive memory design with incomplete data mapping.” in IEEE International Conference on Computer Design (ICCD), Nov. 2013, pp. 131-137.
Chang, M.-F., et al., “A low-voltage bulk-drain-driven read scheme for sub-0.5 V 4 Mb 65 nm logic-process compatible embedded resistive RAM (ReRAM) macro.” IEEE J. Solid-State Circuits, vol. 48, pp. 2250-2259, Sep. 2013.
Chang, M.-F., et al., “Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations”. IEEE J, of Solid-State Circuits, vol. 50, pp. 2786-2795, Sep. 2015.
Meena, J.S., et al., “Overview of emerging non-volatile memory technologies.” Nanoscale research letters, Sep. 2014, pp. 1-33.
Niu, D., et al. “Low power multi-level-cell resistive memory design with incomplete data mapping.” in IEEE International Conference on Computer Design (ICCD), Nov. 2013, pp. 131-137.
Chang, M.-F., et al., “A low-voltage bulk-drain-driven read scheme for sub-0.5 V 4 Mb 65 nm logic-process compatible embedded resistive RAM (ReRAM) macro.” IEEE J. Solid-State Circuits, vol. 48, pp. 2250-2259, Sep. 2013.
Chang, M.-F., et al., “Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations”. IEEE J, of Solid-State Circuits, vol. 50, pp. 2786-2795, Sep. 2015.
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