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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- Korean Society for Precision Engineering Journal of the Korean Society for Precision Engineering Journal of the Korean Society for Precision Engineering Vol.41 No.6
- 발행연도
- 2024.6
- 수록면
- 467 - 472 (6page)
- DOI
- 10.7736/JKSPE.024.027
이용수
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초록· 키워드
오류제보하기
Chemical mechanical planarization (CMP) is an essential polishing process in semiconductor manufacturing. Advances in memory technology, including increased capacity and performance, have increased the importance of electronic packaging. In heterogeneous integration, the interposer acts as an important intermediary between the logic die and the substrate, solving numerous I/O bump problems in high-bandwidth memory (HBM) and logic chips. Traditionally, board-to-memory connections were made through wire bonding, which required additional space for wire connections and introduced latency due to extended signal transmission paths. A through-type approach has emerged as a solution that can significantly reduce waiting time and installation space by improving space efficiency and enabling vertical connections without extending wiring. Due to these new approaches, the importance of CMP is reemerging. Implementation of this important process requires precise control of the CMP dishing/protrusion of bonding surfaces. Improper selection of Cu pad dishing/protrusion can cause problems such as increased RC delay time and signal short circuit in the wiring. In this paper, we proposed a strategy to control dishing using CMP, especially for Through-glass-via (TGV).
목차
1. 서론
2. 이론적 배경
3. 실험
4. 결론
REFERENCES
참고문헌 (15)
참고문헌 신청
Wong, H., (2021), On the CMOS device downsizing, more moore, more than moore, and more-than-moore for more moore, Proceedings of the 2021 IEEE 32nd International Conference on Microelectronics (MIEL), 9-15.
Suzano, J., Abouzeid, F., Natale, G. D., Philippe, A., Roche, P., (2023), On hardware security and trust for chiplet-based 2.5D and 3D ICs: challenges and innovations, IEEE Access, 12, 29778-29794.
Jang, J.-G., Suk, K.-L., Lee, S.-H., Park, J.-W., Jeon, G.-J., Park, J.-H., Jin, J.-G., Lee, S.-C., Kim, G.-B., Choi, J.-Y., (2020), Advanced RDL interposer PKG technology for heterogeneous integration, Proceedings of the 2020 International Wafer Level Packaging Conference (IWLPC), pp. 1-5.
Liu, Z., Fu, H., Hunegnaw, S., Wang, J., Merschky, M., Magaya, T., Mieno, A., Shorey, A., Kuramochi, S., Akazawa, M., Yun, H., (2016), Electroless and electrolytic copper plating of glass interposer combined with metal oxide adhesion layer for manufacturing 3D RF devices, Proceedings of the 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 62-67.
He, H., Xue, H., Sun, Y., Liu, F., Cao, L., (2022), Design and realization of multi-channel and high-bandwidth 2.5D transmitter integrated with silicon photonic MZM, Journal of Lightwave Technology, 40(15), 5201-5215.
Suzano, J., Abouzeid, F., Natale, G. D., Philippe, A., Roche, P., (2023), On hardware security and trust for chiplet-based 2.5D and 3D ICs: challenges and innovations, IEEE Access, 12, 29778-29794.
Jang, J.-G., Suk, K.-L., Lee, S.-H., Park, J.-W., Jeon, G.-J., Park, J.-H., Jin, J.-G., Lee, S.-C., Kim, G.-B., Choi, J.-Y., (2020), Advanced RDL interposer PKG technology for heterogeneous integration, Proceedings of the 2020 International Wafer Level Packaging Conference (IWLPC), pp. 1-5.
Liu, Z., Fu, H., Hunegnaw, S., Wang, J., Merschky, M., Magaya, T., Mieno, A., Shorey, A., Kuramochi, S., Akazawa, M., Yun, H., (2016), Electroless and electrolytic copper plating of glass interposer combined with metal oxide adhesion layer for manufacturing 3D RF devices, Proceedings of the 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 62-67.
He, H., Xue, H., Sun, Y., Liu, F., Cao, L., (2022), Design and realization of multi-channel and high-bandwidth 2.5D transmitter integrated with silicon photonic MZM, Journal of Lightwave Technology, 40(15), 5201-5215.
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